LX64V-5FN100C Lattice, LX64V-5FN100C Datasheet - Page 70

• Manufacturer Part Number: LX64V-5FN100C
• Description: Analog & Digital Crosspoint ICs 64 I/O Switch Matrix, 3.3V, SERDES, 5ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX64V-5FN100C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 64 x 64
• Package / Case: FPBGA-100
• Data Rate: 11 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispGDX2-256 Logic Signal Connections (Continued)
TOE
1. The signals in this column route to/from the assigned pins of the associated I/O cell.
2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When
3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in
4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected.
5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not avail-
6. FIFO_STRDb flag output is used in SERDES with FIFO Mode only.
7. sysHSI Source Synchronous Receive Mode is not available for channel 3A.
Signal
transmit data (TXD) is present in the cell, the associated pin is available for input only.
FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY flags are routed to the associated pins through the output MUX and
the pins.
able for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for
transmitter.
Name
sysIO
Bank
-
Pair/Polarity
LVDS
-
Block MRB
GDX
-
-
SERDES Mode
I/O Pin
-
1
67
SERDES Mode
I/O Cell
-
2
ispGDX2 Family Data Sheet
FIFO Mode I/O
Cell/Pin
-
3
fpBGA
AB10
484