PCK351D NXP Semiconductors, PCK351D Datasheet - Page 8

• Manufacturer Part Number: PCK351D
• Description: Clock Buffer 1:10 CLK DISTR DEV 3-ST OUTPUT
• Manufacturer: NXP Semiconductors

Specifications of PCK351D

• Number Of Outputs: 10
• Propagation Delay (max): 4.1 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Power Dissipation: 650 mW
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SO-24
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 6.3ns
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Pin Count: 24
• Operating Supply Voltage (typ): 3.3V
• Package Type: SO
• Quiescent Current: 25mA
• Power Dissipation: 650mW
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PCK351D,112

Philips Semiconductors
Table 8:
GND = 0 V; t
PCK351_2
Product data sheet
Symbol Parameter
V
t
t
t
t
t
t
t
t
t
t
t
V
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
sk(p)
sk(pr)
r
f
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
sk(p)
sk(pr)
r
f
CC
CC
= 3.3 V; T
= 3.0 V to 3.6 V; T
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
OFF-state to HIGH propagation delay OE to Yn; see
OFF-state to LOW propagation delay OE to Yn; see
HIGH to OFF-state propagation delay OE to Yn; see
LOW to OFF-state propagation delay OE to Yn; see
output skew time
pulse skew time
process skew time
rise time
fall time
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
OFF-state to HIGH propagation delay OE to Yn; see
OFF-state to LOW propagation delay OE to Yn; see
HIGH to OFF-state propagation delay OE to Yn; see
LOW to OFF-state propagation delay OE to Yn; see
output skew time
pulse skew time
process skew time
rise time
fall time
Dynamic characteristics
r
= t
amb
f
= 25 C; C
2.5 ns.
amb
= 40 C to +85 C; C
L
= 50 pF
Rev. 02 — 16 December 2005
Conditions
A to Yn; see
A to Yn; see
A to Yn; output-to-output;
see
A to Yn; see
A to Yn; part-to-part;
see
A to Yn; see
A to Yn; see
A to Yn; see
A to Yn; see
A to Yn; output-to-output;
see
A to Yn; see
A to Yn; part-to-part;
see
A to Yn; see
A to Yn; see
L
= 50 pF
Figure 7
Figure 7
Figure 7
Figure 7
Figure 5
Figure 5
Figure 7
Figure 5
Figure 5
Figure 5
Figure 5
Figure 7
Figure 5
Figure 5
and
and
and
and
1 : 10 clock distribution device with 3-state outputs
Figure 6
Figure 6
Figure 6
Figure 6
Figure 6
Figure 6
Figure 6
Figure 6
Figure 8
Figure 8
Figure 8
Figure 8
and
and
and
and
and
and
and
and
and
and
and
and
and
and
and
and
and
and
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Min
3.1
3.1
1.8
1.8
1.8
1.8
-
-
-
0.3
0.3
2.5
2.5
1.3
1.3
1.7
1.7
-
-
-
0.3
0.3
Typ
3.8
3.8
3.8
3.8
3.8
3.8
0.3
0.2
-
-
-
3.3
3.3
-
-
-
-
-
-
-
-
-
PCK351
4.1
4.1
5.5
5.5
5.9
5.9
0.5
0.8
1
2.0
2.0
5.9
5.9
5.9
5.9
6.3
6.3
0.5
0.8
1
2.0
2.0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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