DS1307ZN+T&R/C02 Maxim Integrated Products, DS1307ZN+T&R/C02 Datasheet - Page 3
![no-image](/images/manufacturer_photos/0/4/417/maxim_integrated_products_sml.jpg)
DS1307ZN+T&R/C02
Manufacturer Part Number
DS1307ZN+T&R/C02
Description
Real Time Clock 64 x 8 I2C-Compatibl e Real Time Clock I2
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1307Z.pdf
(14 pages)
Specifications of DS1307ZN+T&R/C02
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AC ELECTRICAL CHARACTERISTICS
(V
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START
Condition
LOW Period of SCL Clock
HIGH Period of SCL Clock
Setup Time for a Repeated START
Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
Setup Time for STOP Condition
CAPACITANCE
(T
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Pin Capacitance (SDA, SCL)
Capacitance Load for Each Bus
Line
A
CC
= +25°C)
= 4.5V to 5.5V; T
PARAMETER
All voltages are referenced to ground.
Limits at -40°C are guaranteed by design and are not production tested.
I
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
C
PARAMETER
CCS
B
—total capacitance of one bus line in pF.
specified with V
A
HD:DAT
= 0°C to +70°C, T
CC
only has to be met if the device does not stretch the LOW period (t
= 5.0V and SDA, SCL = 5.0V.
SYMBOL
SYMBOL
t
t
t
t
t
HD:STA
SU:STA
HD:DAT
SU:DAT
SU:STO
t
t
f
t
C
HIGH
LOW
C
BUF
SCL
t
t
R
I/O
F
B
A
= -40°C to +85°C.)
(Note 4)
(Notes 5, 6)
(Note 7)
3 of 14
CONDITIONS
CONDITIONS
DS1307 64 x 8, Serial, I
MIN
MIN
250
4.7
4.0
4.7
4.0
4.7
4.7
0
0
TYP
TYP
LOW
) of the SCL signal.
2
C Real-Time Clock
MAX
1000
MAX
100
300
400
10
IH(MIN)
of the SCL
UNITS
UNITS
kHz
pF
pF
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs