CY28800OXCT Silicon Laboratories Inc, CY28800OXCT Datasheet - Page 7

• Manufacturer Part Number: CY28800OXCT
• Description: Clock Buffer PCI Express & Sata Diff Buffer 100MHz
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28800OXCT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
Table 4. Buffer Power-up State Machine
SRC_STP Clarification
The SRC_STP signal is an asynchronous input used for clean
stopping and starting the DIFT/C outputs. This input can be
Active High or Active Low based on the strapped value of the
OE_INV input. The SRC_STP signal is a debounced signal in
that its state must remain unchanged during two consecutive
rising edges of DIFC to be recognized as a valid assertion or
deassertion. (The assertion and deassertion of this signal is
absolutely asynchronous.) In the case where the output is
Notes:
1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN is an undefined mode and not recommended. Operation in this mode may result in glitches
2. The total power-up latency from power on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input).
3. LOCK output is a latched signal that is reset with the assertion of PWRDWN or when VDD<1.8V.
4. Special care must be taken to ensure that no abnormal clock behavior occurs after the assertion PLL LOCK (i.e., overshoot/undershoot is allowed).
5. In PLL mode, if power is valid and PWRDWN is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid
6. In the case where OE is asserted low, the output will always be three-stated regardless of SRC_STP drive mode register bit state.
3
State
excessive frequency shifting.
input clocks are detected, valid power, PWRDWN deasserted with the PLL locked and stable, are the DIF outputs enabled.
[2, 3, 4]
2
0
1
[5]
3.3V Buffer power off
After 3.3V supply is detected to rise above 1.8V–2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay
Buffer waits for PWRDWN deassertion (and a valid clock on the SRC_IN input if in PLL mode)
Outputs enabled for normal operation (PLL lock to the SRC_IN input is assured in PLL mode)
PWRDWN
DIFC
DIFT
Figure 4. PWRDWN Deassertion Diagram, OE_INV = 1
Figure 5. Buffer Power-up State Diagram
<300 μs, >200 mV
Tdrive_Pwrdwn#
Tstable
<1 ms
Description
disabled via OE control, the output will always be tri-stated
regardless of the SRC_STP Drive Mode register bit state.
Table 5. SRC_STP Functionality
OE_INV
0
0
1
1
SRC_STP
[1]
1
0
1
0
Iref * 6 or Float
Iref * 6 or Float
[6]
Normal
Normal
DIFT
CY28800
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Normal
Normal
DIFC
Low
Low