CY28800OXCT Silicon Laboratories Inc, CY28800OXCT Datasheet
CY28800OXCT
Specifications of CY28800OXCT
Related parts for CY28800OXCT
CY28800OXCT Summary of contents
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Differential Buffer for PCI Express and SATA Features • CK409 and CK410 companion buffer • Eight differential 0.7V clock output pairs • OE_INV input for inverting OE, PWRDWN, and SRC_STP active levels • Individual OE controls • Low CTC ...
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Pin Description Pin 4,5 SRCT_IN, SRCC_IN 8,9;12,13;16,17;20,21; 30,29; DIF[T/C][7:0] 34,33;38,37;42,41 6,7,14,15,35,36,43,44 OE_[7:0] 28 HIGH_BW# 45 LOCK 26 PWRDWN 1 SRC_DIV2# 27 SRC_STP 23 SCLK 24 SDATA 46 IREF 22 PLL/BYPASS# 48 VDD_A 47 VSS_A 3,10,18,25,32 VSS 2,11,19,31,39 VDD 40 OE_INV ...
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Table 2. Block Read and Block Write Protocol Block Write Protocol Bit Description 1 Start 2:8 Slave address – 7 bits 9 Write = 0 10 Acknowledge from slave 11:18 Command Code – 8 bits '00000000' stands for block operation ...
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Byte 0: Control Register 0 Bit @pup Name 7 0 PWRDWN Drive Mode 6 0 SRC_STP Drive Mode 5 0 Reserved 4 0 Reserved 3 0 Reserved 2 1 HIGH_BW PLL/BYPASS SRC_DIV2# Byte 1: Control Register ...
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Byte 2: Control Register 2 (continued) Bit @pup Name 4 0 SRC_STP_DIF[T/C SRC_STP_DIF[T/C SRC_STP_DIF[T/C SRC_STP_DIF[T/C SRC_STP_DIF[T/C]0 Byte 3: Control Register 3 Bit @pup Name ...
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OE_INV Clarification The OE_INV pin is an input strap sampled at power-on. The functionality of this input is to set the active level polarities for OE_[7:0], PWRDWN, and SRC_STP input pins. ‘Active High’ indicates the functionality of the input is ...
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PWRDWN DIFT DIFC Figure 4. PWRDWN Deassertion Diagram, OE_INV = 1 Table 4. Buffer Power-up State Machine State 0 3.3V Buffer power off 1 After 3.3V supply is detected to rise above 1.8V–2.0V, the buffer enters state 1 and initiates ...
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SRC_STP Assertion The impact of asserting the SRC_STP pin is that all DIF outputs that are set in the control registers to stoppable via assertion of SRC_STP are stopped after their next transition. When the control register SRC_STP three-state bit ...
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SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 9. SRC_STP = Driven, PWRDWN = Driven, OE_INV = 1 SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 10. SRC_STP = Tri-state, PWRDWN = Driven, OE_INV ...
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OE Assertion All differential outputs that were tri-stated will resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2–6 DIF clock periods. In addition, DIFT clocks will be driven high within ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J ESD ESD Protection (Human Body Model) HBM UL-94 ...
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AC Electrical Specifications (continued)(Measured in High Bandwidth Mode) Parameter Description ΔV Vcross Variation over all edges OX V Differential Ringback Voltage RB T Time before ringback allowed STABLE V Absolute maximum input voltage MAX V Absolute minimum input voltage MIN ...
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Switching Waveforms V = 0.525V OH VCROSS V = 0.175V OL Figure 13. Single-Ended Measurement Points for TRise and TFall Figure 14. Single-ended Measurement Points for V Rev 1.0, November 21, 2006 CY28800 TRise (CLOCK) ...
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Skew Management Point 0.000V Figure 15. Differential (Clock-Clock#) Measurement Points (Tperiod, Duty Cycle and Jitter) Rev 1.0, November 21, 2006 T PERIOD High Duty Cycle % CY28800 Low Duty Cycle % Page ...
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... Ordering Code Lead Free CY28800OXC CY28800OXCT Package Drawing and Dimensions While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in ...