PCA8802CX8/B/1,027 NXP Semiconductors, PCA8802CX8/B/1,027 Datasheet - Page 15

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PCA8802CX8/B/1,027

Manufacturer Part Number
PCA8802CX8/B/1,027
Description
Real Time Clock ultra LOW POWER OSC Smartcard RTC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA8802CX8/B/1,027

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935288465027
NXP Semiconductors
PCA8802_1
Product data sheet
9.6.4 Instruction pwd_cmd
When the dividers are restarted, the first increment of the 24 bit counter will be after 32
seconds.
When the dividers are restarted, the 8192 Hz clock could have just occurred and hence a
delay of
8192 Hz clock could be just about to occur and immediately increment the divider_2. As a
consequence, an uncertainty of one half clock period will be present when restarting (see
Figure
The power down instruction (pwd_cmd) is intended to be used to put the system into a low
power mode for storage. Static leakage current will be the only power consumed. Storage
at temperatures above room temperature may increase leakage currents.
Entering power-down requires a specific sequence of events since under normal
circumstances stopping the oscillator would result in a chip reset.
Fig 24. Instruction dvs_cmd
32.768 kHz
24).
1
Divider_1 = dividing by 4.
Divider_2 = dividing by 8192.
Divider_3 = dividing by 32.
8192
seconds will occur before the next increment of the divider_2, or the
DIVIDER_1
dvs_cmd disable
Rev. 01 — 19 February 2009
8.192 kHz
8.192 kHz
counter
first increment after dvs_cmd disable
DIVIDER_2
will be after 32 seconds ±61 s
dvs_cmd
reset
1 Hz
DIVIDER_3
reset
1/32 Hz
PCA8802
© NXP B.V. 2009. All rights reserved.
Smartcard RTC
clock
COUNTER
24 BIT
001aaj170
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