CY28400OC Silicon Laboratories Inc, CY28400OC Datasheet - Page 5

• Manufacturer Part Number: CY28400OC
• Description: Clock Buffer 100 MHz Diff Buffer PCI Express & SATA
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28400OC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
Byte 4: Vendor ID Register
Byte 5: Control Register 5
PWRDWN# Clarification
The PWRDWN# pin is used to shut off all clocks cleanly and
instruct the device to evoke power savings mode. Additionally,
PWRDWN# should be asserted prior to shutting off the input
clock or power to ensure all clocks shut down in a glitch-free
manner. PWRDWN# is an asynchronous active LOW input.
This signal is synchronized internal to the device prior to
powering down the clock buffer. PWRDWN# is an
When PWRDWN# is sampled LOW by two consecutive rising edges of DIFC, all DIFT outputs will be held HIGH or three-stated
(depending on the state of the control register drive mode and OE bits) on the next DIFC HIGH-to-LOW transition. When the
SMBus power-down drive mode bit is programmed to ‘0’, all clock outputs will be held with the DIFT pin driven HIGH at 2 x Iref
and DIFC three-state. However, if the control register PWRDWN# drive mode bit is programmed to ‘1’, then both DIFT and the
DIFC are three-stated.
Note:
1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN# is an undefined mode and not recommended. Operation in this mode may result in glitches
excessive frequency shifting.
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
PWRDWN#
DIFC
DIFT
[1]
Name
Name
Figure 1. PWRDWN# Assertion Diagram
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
asynchronous input for powering up the system. When
PWRDWN# is asserted LOW, all clocks will be held HIGH or
three-stated (depending on the state of the control register
drive mode and OE bits) prior to turning off the VCO. All clocks
will start and stop without any abnormal behavior and must
meet all AC and DC parameters. This means no glitches,
frequency shifting or amplitude abnormalities among others.
PWRDWN# Assertion
Description
Description
CY28400
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