CY28400OC Silicon Laboratories Inc, CY28400OC Datasheet - Page 2

• Manufacturer Part Number: CY28400OC
• Description: Clock Buffer 100 MHz Diff Buffer PCI Express & SATA
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28400OC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
Pin Descriptions
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Table 1. Command Code Definition
Table 2. Block Read and Block Write Protocol
2,3
6,7,9,10,19,20,22,23
8,21
17
16
15
13
14
26
12
28
27
4,25
1,5,11,18,24
11:18
(6:0)
2:8
Bit
Bit
10
19
7
1
9
Pin
Slave address – 7 bits
Command Code – 8 bits
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Start
Write = 0
Acknowledge from slave
'00000000' stands for block operation
Acknowledge from slave
Block Write Protocol
SRCT_IN, SRCC_IN
DIFT/C(2:1) & (6:5)
OE_1, OE_6
HIGH_BW#
SRC_STOP#
PWRDWN#
SCLK
SDATA
IREF
PLL/BYPASS#
VDD_A
VSS_A
VSS
VDD
Name
Description
I,DIF
O,DIF
I,SE
I,SE
I,SE
I,SE
I,SE
I/O,OC
I
I
3.3V
GND
3.3V
GND
Type
0.7V differential SRC inputs from the clock synthesizer
0.7V differential clock outputs
3.3V LVTTL active LOW input for three-stating differential
outputs (DIFT2 and DIFT5 are unaffected by the assertion of OE
inputs)
3.3V LVTTL input for selecting PLL bandwidth
3.3V LVTTL input for SRC_STOP#, active LOW
3.3V LVTTL input for Power Down, active LOW
SMBus slave clock input
Open collector SMBus data
A precision resistor is attached to this pin to set the differential
output current
3.3V LVTTL input for selecting fan-out or PLL operation
3.3V power supply for PLL
Ground for PLL
Ground for outputs
3.3V power supply for outputs
Description
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11011100 (DCh).
11:18
2:8
Bit
10
19
1
9
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Block Read Protocol
Description
Description
CY28400
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