CY2SSTV857ZXC-32 Silicon Laboratories Inc, CY2SSTV857ZXC-32 Datasheet - Page 2

• Manufacturer Part Number: CY2SSTV857ZXC-32
• Description: Clock Buffer 2.5V 60-200MHz 1:10 Diff DDR266/333 B/D
• Manufacturer: Silicon Laboratories Inc

Specifications of CY2SSTV857ZXC-32

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
Pin Description
13, 14
35
36
3, 5, 10, 20, 22
2, 6, 9, 19, 23
27, 29, 39, 44, 46 17,19,29,32,34
26, 30, 40, 43, 47 16,20,30,31,35
32
33
37
4, 11,12,15, 21,
28, 34, 38, 45
16
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
17
Note:
1. A bypass capacitor (0.1μF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
48 TSSOP
Pin #
5,6
25
26
37,39,3,12,14
36,40,2,11,15
21
22
27
4,7,13,18,23,24,
28,33,38
8
1,10
9
40 QFN
Pin #
VDDQ
VDDQ
AVDD
AVSS
CLK#
CLK, CLK#
CLK
Pin Name
VSS
VSS
Y2#
FBOUT#
FBOUT
Y2
Y#(0:4)
Y#(9:5)
FBIN#
VDDQ
Y(0:4)
Y(9:5)
AVDD
AVSS
FBIN
VSS
PD#
10
4
5
6
7
8
9
1
2
3
40
11
39
12
I/O
O
O
O
O
O
O
40 QFN Package
CY2SSTV857-32
I
I
I
I
38
13
[1]
37
14
40 QFN
Differential Clock Input.
Feedback Clock Input. Connect to FBOUT# for
accessing the PLL.
Feedback Clock Input. Connect to FBOUT for
accessing the PLL.
Clock Outputs.
Clock Outputs.
Clock Outputs.
Clock Outputs.
Feedback Clock Output. Connect to FBIN for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
Feedback Clock Output. Connect to FBIN# for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
Power Down Input. When PD# is set HIGH, all
Q and Q# outputs are enabled and switch at the
same frequency as CLK. When set LOW, all Q
and Q# outputs are disabled Hi-Z and the PLL
is powered down.
2.6V Power Supply for Output Clock Buffers. 2.6V Nominal
2.6V Power Supply for PLL. When VDDA is at
GND, PLL is bypassed and CLK is buffered
directly to the device outputs. During disable
(PD# = 0), the PLL is powered down.
Common Ground.
Analog Ground.
15
36
16
35
17
34
18
33
19
32
Pin Description
20
31
21
27
26
25
24
23
22
30
29
28
Y7#
Y7
VDDQ
PD#
FBIN
FBIN#
VDDQ
VDDQ
FBOUT#
FBOUT
CY2SSTV857-32
LV Differential Input
Differential Input
Differential Outputs
Differential Outputs
Differential Outputs
2.6V Nominal
0.0V Ground
0.0V Analog
Ground
Characteristics
Page 2 of 8
Electrical