M41ST84YMQ6 STMicroelectronics, M41ST84YMQ6 Datasheet - Page 16

• Manufacturer Part Number: M41ST84YMQ6
• Description: Real Time Clock Serial 512 (64x8)
• Manufacturer: STMicroelectronics

Specifications of M41ST84YMQ6

• Function: Clock, Calendar, Supervisor
• Rtc Memory Size: 64 B
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial
• Package / Case: SO-16
• Time Format: HH:MM:SS:hh
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operating modes
2.3
2.4
Figure 11. WRITE mode sequence
16/34
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
WRITE mode
In this mode the master transmitter transmits to the M41ST84W slave receiver. Bus protocol
is shown in
is placed on the bus and indicates to the addressed device that word address An will follow
and is to be written to the on-chip address pointer. The data word to be written to the
memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41ST84W
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address (see
address and each data byte.
Data retention mode
With valid V
WRITE cycles. Should the supply voltage decay, the M41ST84W will automatically deselect,
write protecting itself when V
accomplished by internally inhibiting access to the clock registers. At this time, the Reset pin
(RST) is driven active and will remain active until V
falls below the battery backup switchover voltage (V
V
attached battery supply.
All outputs become high impedance. On power up, when V
write protection continues for t
Figure 18 on page
For a further more detailed review of lifetime calculations, please see application note
AN1012.
CC
pin to the external battery, and the clock registers and SRAM are maintained from the
S
ADDRESS
Figure
CC
SLAVE
applied, the M41ST84W can be accessed as described above with READ or
11. Following the START condition and slave address, a logic '0' (R/W=0)
30).
Figure 8 on page
ADDRESS (An)
WORD
CC
rec
falls between V
. The RST signal also remains active during this time (see
14) and again after it has received the word
DATA n
PFD
CC
(max) and V
SO
returns to nominal levels. When V
), power input is switched from the
DATA n+1
CC
returns to a nominal value,
PFD
(min). This is
DATA n+X
AI00591
M41ST84W
P
CC