ispPAC-CLK5304S-01TN48I Lattice, ispPAC-CLK5304S-01TN48I Datasheet - Page 21

• Manufacturer Part Number: ispPAC-CLK5304S-01TN48I
• Description: Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ispPAC-CLK5304S-01TN48I

• Max Input Freq: 267 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 14. Input Receiver Termination Configuration
Feedback input is terminated to the VTT_FBK pin through a programmable resistor.
The following usage guidelines are suggested for interfacing to supported logic families.
REFA_REFP
REFB_REFN
VTT_REFA
VTT_REFB
R T
R T
Single-ended
Single-ended
21
Differential
Receiver
Receiver
Receiver
+
–
ispClock5300S Family Data Sheet
Internal
Logic
To