WM8983GEFL/RV Wolfson Microelectronics, WM8983GEFL/RV Datasheet - Page 87

• Manufacturer Part Number: WM8983GEFL/RV
• Description: Audio CODECs Mbl Multimedia CODEC w/ 1W Speaker Driver
• Manufacturer: Wolfson Microelectronics

Specifications of WM8983GEFL/RV

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C

Production Data
Table 60 PLL Frequency Examples for Common MCLK Rates
w
(MHz)
MCLK
19.68
19.68
14.4
14.4
19.2
19.2
19.8
19.8
(F1)
12
12
13
13
24
24
26
26
27
27
DESIRED
OUTPUT
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
(MHz)
11.29
11.29
11.29
11.29
11.29
11.29
11.29
11.29
11.29
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
(MHz)
F2
Table 59 PLL Frequency Ratio Control
The PLL performs best when f
are shown in Table 60.
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data
from the ADC audio interface is fed directly into the DAC data input.
R36
PLL N value
R37
PLL K value
1
R38
PLL K Value
2
R39
PLL K Value
3
REGISTER
ADDRESS
PRESCALE
DIVIDE
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
4
3:0
5:0
8:0
8:0
BIT
MCLKDIV
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PLLPRESCALE
PLLN
PLLK [23:18]
PLLK [17:9]
PLLK [8:0]
2
LABEL
is around 90MHz. Its stability peaks at N=8. Some example settings
6.947446
7.561846
6.826667
9.178537
9.990243
9.122909
9.929697
6.947446
7.561846
6.690133
7.281778
7.5264
7.5264
8.192
6.272
9.408
10.24
8.192
R
(Hex)
PLLN
R36
A
7
8
6
7
6
6
9
9
9
9
9
7
8
6
7
6
7
0
1000
0Ch
093h
0E9h
DEFAULT
BOAC93
F28BD4
45A1CA
D3A06E
3D70A3
2DB492
EE009E
F28BD4
86C226
8FD525
6872AF
FD809F
86C226
8FD525
3126E8
1F76F7
3126E8
482296
(Hex)
K
R37 (Hex)
1 = Divide MCLK by 2 before input
to PLL
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
0 = MCLK input not divided (default)
[23:18]
PLLK
3C
3C
2C
21
23
11
34
1A
3F
3B
21
23
12
C
B
C
F
7
PD Rev 4.0 November 2006
DESCRIPTION
R38 (Hex)
PLLK
[17:9]
1EA
1BB
1EA
1D0
161
145
100
161
145
DA
D0
B8
C0
93
39
93
56
11
WM8983
R39 (Hex)
PLLK
[8:0]
1CA
1D4
1D4
126
126
6D
26
E9
B0
A3
92
9F
F8
9E
26
E9
94
96
87