MAX194ACWE Maxim Integrated Products, MAX194ACWE Datasheet - Page 17

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MAX194ACWE

Manufacturer Part Number
MAX194ACWE
Description
Audio A/D Converter ICs
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX194ACWE

Conversion Rate
85 KSPs
Resolution
14 bit
Number Of Adc Inputs
1
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MAX194ACWE
Manufacturer:
MAXIM/美信
Quantity:
20 000
Figure 18. Timing Diagram for Circuit of Figure 17
Figure 19. MAX194 Connection to QSPI Processor Clocking
Data Out with SCLK Between Conversions
MicroWire is a trademark of National Semiconductor Corp.
START
QSPI
GPT
CS, CONV
IC3
DOUT
DATA LATCHED:
EOC
CLK
PCS0
MISO
SCK
OC3
OC2
IC1
1.3 s
14-Bit, 85ksps ADC with 10µA Shutdown
______________________________________________________________________________________
t
DV
B13 FROM PREVIOUS
74HC32
CONVERSION
CS
SCLK
DOUT
BP/UP/SHDN
EOC
RESET
CONV
MAX194
CLK
B13
t
CD
1.7MHz
B12
Data is clocked out of the MAX194 on CLK’s falling
edge and can be clocked into the µP on the rising
edge or the following falling edge. If you clock data in
on the rising edge (SPI/QSPI with CPOL = 0 and CPHA
= 0; standard MicroWire™: Hitachi H8), the maximum
CLK rate is given by:
where t
and t
If clocking data in on the falling edge (CPOL = 0,
CPHA = 1), the maximum CLK rate is given by:
Do not exceed the maximum CLK frequency given in
the Electrical Characteristics table. To clock data in on
the falling edge, your processor hold time must not
exceed t
While QSPI can provide the required 20 CLK cycles as
two continuous 10-bit transfers, SPI is limited to 8-bit
transfers. This means that with SPI, a conversion must
consist of three 8-bit transfers. Ensure that the pauses
between 8-bit operations at your selected clock rate
are short enough to maintain a 20ms or shorter conver-
sion time, or the leakage of the capacitive DAC may
cause errors.
B0
SD
CD
is the data setup time for your µP.
S1
CD
f
is the MAX194’s CLK-to-DOUT valid delay
CLK(max)
minimum (100ns).
S0
f
CLK(max)
= /
1
=
2
B13
t
CD
t
CD
+ t
1
+ t
1
SD
SD
t
DH
17

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