WM8973LGEFL/V Wolfson Microelectronics, WM8973LGEFL/V Datasheet - Page 21

• Manufacturer Part Number: WM8973LGEFL/V
• Description: Audio CODECs Stereo Codec with H/P Spkr
• Manufacturer: Wolfson Microelectronics

Specifications of WM8973LGEFL/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced Information
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Table 9 ADC Signal Path Control
Table 10 ADC Highpass Filter Enable Modes
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally amplified or attenuated over a range from –97dB to +30dB in
0.5dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit
code X is given by:
0.5
The LAVU and RAVU control bits control the loading of digital volume control data. When LAVU or
RAVU are set to 0, the LADCVOL or RADCVOL control data will be loaded into the respective control
register, but will not actually change the digital gain setting. Both left and right gain settings are
updated when either LAVU or RAVU are set to 1. This makes it possible to update the gain of both
channels simultaneously.
HPFLREN
R5 (05h)
ADC and DAC
Control
R27 (1Bh)
(X-195) dB for 1
0
0
1
1
REGISTER
ADDRESS
ADCHPD
0
1
0
1
6:5
4
0
5
BIT
X
Highpass Filter enabled on left and
right channels
Highpass Filter disabled on left and
right channels
Highpass filter enabled on left
channel, disabled on right channel
Highpass filter disabled on left
channel, enabled on right channel
255;
ADCPOL
[1:0]
HPOR
ADCHPD
HPFLREN
LABEL
HIGHPASS MODE
MUTE for X = 0
00
0
0
0
DEFAULT
00 = Polarity not inverted
01 = L polarity invert
10 = R polarity invert
11 = L and R polarity invert
Store dc offset when High Pass
Filter disabled
1 = store offset
0 = clear offset
ADC High Pass Filter Enable
(Digital)
HPFLREN = 0
1 = Disable High Pass Filter on
left and right channels
0 = Enable High Pass Filter on left
and right channels
HPFLREN = 1
0 = Highpass enabled on left,
disabled on right
1 = Highpass enabled on right,
disabled on left
ADC highpass filter left or right
enable
0 = Highpass filter enable/disable
on left and right channels
controlled by ADCHPD
1 = Highpass filter enabled on left
or right channel, as selected by
ADCHPD
DESCRIPTION
AI Rev 3.2 July 2004
WM8973L
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