HSP45106JC-25 Intersil, HSP45106JC-25 Datasheet - Page 4
![no-image](/images/manufacturer_photos/0/3/341/intersil_sml.jpg)
HSP45106JC-25
Manufacturer Part Number
HSP45106JC-25
Description
Manufacturer
Intersil
Datasheet
1.HSP45106JC-25.pdf
(15 pages)
Specifications of HSP45106JC-25
Mounting Style
Surface Mount
Screening Level
Commercial
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HSP45106JC-25
Manufacturer:
HARRIS
Quantity:
20 000
Company:
Part Number:
HSP45106JC-25Z
Manufacturer:
Intersil
Quantity:
90
HSP45106
Functional Description
The 16-bit Numerically Controlled Oscillator (NCO16)
produces a digital complex sinusoid waveform whose
frequency and phase are controlled through a standard
microprocessor interface and discrete inputs. The NCO16
generates 16-bit sine and cosine vectors at a maximum
sample rate of 33MHz. The NCO16 can be preprogrammed
to produce a constant (CW) sine and cosine output for Direct
Digital Synthesis (DDS) applications. Alternatively, the phase
and frequency inputs can be updated in real time to produce
a FM, PSK, FSK, or MSK modulated waveform. To simplify
PSK generation, a 3 pin interface is provided to support
modulation of up to 8 levels.
As shown in Figure 1, the HSP45106 Block Diagram, the
NCO16 is comprised of a Phase and Frequency Control
Section (PFCS) and Sine/ Cosine Section. The PFCS stores
the phase and frequency control inputs and uses them to
calculate the phase angle of a rotating complex vector. The
Sine/Cosine Section performs a lookup on this phase and
generates the appropriate amplitude values for the sine and
cosine. These quadrature outputs may be configured as
serial or parallel with either two's complement or offset
binary format.
Phase/Frequency Control Section
The phase and frequency of the quadrature outputs are
controlled by the PFCS (see Figure 1). The PFCS generates
a 32-bit word which represents the instantaneous phase
(Sin/Cos argument) of the sine and cosine waves being
generated. This phase is incremented on the rising edge of
each CLK by the preprogrammed amounts in the phase and
Frequency Control Registers. As the instantaneous phase
32
steps from 0 through full scale (2
- 1), the phase of the
quadrature outputs proceeds from 0° around the unit circle
counter clockwise.
The PFCS is comprised of a Phase Accumulator Section,
Phase Offset adder, Input Section, and a Timer Accumulator
Section. The Phase Accumulator computes the
instantaneous phase angle from user programmed values in
the Center and Offset Frequency Registers. This angle is
then fed into the Phase Offset adder where it is offset by the
preprogrammed value in the Phase Offset Register. The Input
Section routes data from a microprocessor compatible control
bus and discrete input signals into the appropriate configuration
registers. The Timer Accumulator supplies a pulse to mark the
passage of a user programmed period of time.
4
FN2809.8
October 16, 2008