hsp45106 Intersil Corporation, hsp45106 Datasheet
hsp45106
Available stocks
Related parts for hsp45106
hsp45106 Summary of contents
Page 1
... Data Sheet 16-Bit Numerically Controlled Oscillator The Intersil HSP45106 is a high performance 16-bit quadrature Numerically Controlled Oscillator (NCO16). The NCO16 simplifies applications requiring frequency and phase agility such as frequency-hopped modems, PSK modems, spread spectrum communications, and precision signal generators. As shown in the block diagram, the HSP45106 is divided into a Phase/Frequency Control Section (PFCS) and a Sine/Cosine Section ...
Page 2
... COS3 COS2 G COS5 COS4 V COS8 COS9 COS10 D COS12 C COS13 COS15 B COS14 TICO A C0 PIN ‘A1’ HSP45106 85 PIN CPGA TOP VIEW SIN1 SIN3 SIN5 SIN4 SIN9 SIN12 CLK SIN2 V SIN8 SIN10 CC SIN6 SIN7 SIN11 INHOF ENOF REG ...
Page 3
... The lower 13 bits of the phase control are set to zero. These bits are registered when the Phase Offset Register is enabled. 3 HSP45106 84 LEAD PLCC TOP VIEW ...
Page 4
... FM, PSK, FSK, or MSK modulated waveform. To simplify PSK generation pin interface is provided to support modulation levels. As shown in Figure 1, the HSP45106 Block Diagram, the NCO16 is comprised of a Phase and Frequency Control Section (PFCS) and Sine/ Cosine Section. The PFCS stores the phase and frequency control inputs and uses them to calculate the phase angle of a rotating complex vector ...
Page 5
... HSP45106 MUX MUX 1 0 MUX 1 0 MUX 1 0 ...
Page 6
... The frequency of the quadrature outputs is based on the number of clock cycles required to step from 0 to full scale. 6 HSP45106 The number of steps required for this transition depends on the phase increment calculated by the frequency adder. For example, if the Center and Offset Frequency Registers are ...
Page 7
... FIGURE 3. NCO16 PIPELINE DELAY HSP45106 GND MOD0-2 SIN0-15 V PMSEL CC DATA C0-15 COS0- A0-2 CS ENPOREG ENCFREG OES OEC V ENOFREG CC DECODE GND ENPHAC V ENTIGEG CC GND ...
Page 8
... The Timing Diagrams in Figure 7, 8 and 9 show the pipeline delays through the HSP45106 NCO16 from the time that data is applied to the inputs until the outputs are affected by the change. The delay is shown as a number of clock cycles, with no attempt made to accurately represent the setup and hold times or the clock to output delays ...
Page 9
... FIGURE 5. SINE/COSINE SECTION BLOCK DIAGRAM CLK ENPHAC DACSTRB SERIAL DATA OUTPUT FIGURE 6. SERIAL OUTPUT I/O TIMING DIAGRAM CLK CS WRITE WRITE MS INPUT LS INPUT REGISTER REGISTER WR A(2:0) C(15:0) ENCFREG ENOFREG COS(15:0), SIN(15:0) 9 HSP45106 16 COSINE / SINE/COSINE FORMAT 16 SINE ROM CONTROL / ECS BIT TRANSFER DATA TO CENTER OR OFFSET FREQUENCY REGISTER FIGURE 7 ...
Page 10
... CLK WRITE PHASE INPUT REGISTER WR A(2:0) C(15:0) TRANSFER DATA TO PHASE REGISTER ENPOREG COS(15:0), SIN(15:0) CLK MOD0-2 PMSEL TRANSFER DATA TO PHASE REGISTER ENPOREG COS(15:0), SIN(15:0) FIGURE 9. PHASE MODULATION TO OUTPUT DELAY 10 HSP45106 FIGURE 8. PHASE TO OUTPUT DELAY NEW PHASE DATA NEW PHASE DATA ...
Page 11
... Output Capacitance NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for I 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit with switch open and C 11 HSP45106 o Thermal Information C Thermal Resistance (Typical, Note 1) +0.5V PLCC Package ...
Page 12
... If ENOFREG, ENCFREG, ENTIREG, or ENPOREG are active, care must be taken to not violate setup and hold times to these registers when writing data into the chip via the C(15:0) port. 7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. 12 HSP45106 5.0V ±5%, T ...
Page 13
... AC Test Load Circuit SWITCH S1 OPEN FOR I NOTE: Test head capacitance. Waveforms ENABLE/CONTROL SIN(15:0), COS(15:0), TICO (SERIAL MODE ONLY) A(2:0), CS C(15:0) 13 HSP45106 S DUT 1 C (NOTE) L AND I CCSB CCOP EQUIVALENT CIRCUIT CLK t t MCS MCH MOD(2: ECS ECH SIGNALS DSO ...
Page 14
... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 14 HSP45106 1.5V 1. 1.7V 1.3V HIGH IMPEDANCE FIGURE 12 ...