SI7900AEDN-T1-E3 Vishay, SI7900AEDN-T1-E3 Datasheet - Page 2

MOSFET DUAL N-CH 20V 1212-8

SI7900AEDN-T1-E3

Manufacturer Part Number
SI7900AEDN-T1-E3
Description
MOSFET DUAL N-CH 20V 1212-8
Manufacturer
Vishay
Series
TrenchFET®r

Specifications of SI7900AEDN-T1-E3

Fet Type
2 N-Channel (Dual)
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
26 mOhm @ 8.5A, 4.5V
Drain To Source Voltage (vdss)
20V
Current - Continuous Drain (id) @ 25° C
6A
Vgs(th) (max) @ Id
900mV @ 250µA
Gate Charge (qg) @ Vgs
16nC @ 4.5V
Power - Max
1.5W
Mounting Type
Surface Mount
Package / Case
PowerPAK® 1212-8 Dual
Transistor Polarity
N Channel
Continuous Drain Current Id
8.5A
Drain Source Voltage Vds
20V
On Resistance Rds(on)
36mohm
Rds(on) Test Voltage Vgs
12V
Threshold Voltage Vgs Typ
900mV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SI7900AEDN-T1-E3TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI7900AEDN-T1-E3
Manufacturer:
VISHAY
Quantity:
4 189
Part Number:
SI7900AEDN-T1-E3
Manufacturer:
VISHAY/威世
Quantity:
20 000
Company:
Part Number:
SI7900AEDN-T1-E3
Quantity:
5 250
Si7900AEDN
Vishay Siliconix
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
www.vishay.com
2
SPECIFICATIONS T
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-State Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
b
10
8
6
4
2
0
0
Gate-Current vs. Gate-Source Voltage
3
a
a
V
GS
a
- Gate-to-Source Voltage (V)
J
6
= 25 °C, unless otherwise noted
a
9
Symbol
R
V
I
t
t
I
I
DS(on)
V
GS(th)
D(on)
Q
Q
d(on)
d(off)
GSS
DSS
Q
g
12
t
t
SD
fs
gs
gd
r
f
g
15
V
V
I
DS
D
DS
≅ 1 A, V
= 10 V, V
18
V
V
= 20 V, V
V
V
V
V
V
DS
V
DS
DS
V
V
I
DS
S
GS
DD
DS
DS
GS
GS
Test Conditions
= 2.9 A, V
= 0 V, V
= 0 V, V
= V
= 5 V, V
= 4.5 V, I
= 20 V, V
= 10 V, R
= 10 V, I
= 2.5 V, I
= 1.8 V, I
GEN
GS
GS
GS
, I
= 4.5 V, R
= 4.5 V, I
GS
= 0 V, T
GS
D
GS
D
GS
D
GS
= 250 µA
L
= ± 4.5 V
D
D
= ± 12 V
= 8.5 A
= 4.5 V
= 8.5 A
= 10 Ω
= 8 A
= 7 A
= 0 V
= 0 V
10 000
J
D
1000
G
= 85 °C
0.01
= 6.5 A
100
= 6 Ω
0.1
10
1
0
Gate Current vs. Gate-Source Voltage
T
J
= 150 °C
3
V
Min.
0.40
GS
20
- Gate-to-Source Voltage (V)
6
T
J
0.020
0.022
0.026
Typ.
0.65
10.5
0.85
= 25 °C
1.9
1.8
1.3
8.6
4.2
25
S-81544-Rev. C, 07-Jul-08
Document Number: 72287
9
0.026
0.030
0.036
Max.
± 10
1.25
0.9
± 1
1.1
2.0
6.5
20
16
13
1
12
Unit
mA
nC
µA
µA
ns
Ω
V
A
S
V
15

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