LTC4260CSW#TR Linear Technology, LTC4260CSW#TR Datasheet - Page 11

• Manufacturer Part Number: LTC4260CSW#TR
• Description: MS-Hot Swap/High Voltage, 48V Hot Swap Controller With I2C ADC
• Manufacturer: Linear Technology

Specifications of LTC4260CSW#TR

• Family Name: LTC4260
• Package Type: SOIC W
• Operating Supply Voltage (min): 8.5V
• Operating Supply Voltage (max): 80V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
The typical LTC4260 application is in a high availability
system that uses a positive voltage supply to distribute
power to individual cards. The device measures card
voltages and currents and records past and present fault
conditions. The system queries each LTC4260 over the I
periodically and reads the stored information.
The basic LTC4260 application circuit is shown in Fig-
ure 1. External component selection is discussed in detail
in the Design Example section.
Turn-On Sequence
The power supply on a board is controlled by placing an
external N-channel pass transistor (Q1) in the power path.
Note that sense resistor (R
C1 controls the GATE slew rate. Resistor R6 compensates
the current control loop while R5 prevents high frequency
oscillations in Q1. Resistors R1, R2 and R3 provide
undervoltage and overvoltage sensing.
Several conditions must be present before the external
switch can be turned on. First the external supply V
must exceed its undervoltage lockout level. Next the
internally generated supply INTV
undervoltage threshold. This generates a 60µs to 120µs
power-on-reset pulse. During reset the fault registers are
ALERT
GND
SDA
SCL
48V
V
IN
BACKPLANE PLUG-IN
U
CARD
U
S
) detects current and capacitor
CC
Z1*
SMBT70A
W
must cross its 4.5V
*DIODES, INC
C
0.1µF
F
Figure 1. 5A, 48V Card Resident Application
R1
49.9k
1%
R2
1.74k
1%
R3
2.67k
1%
U
10
11
5
7
9
8
OV
ON
SDAI
SDA0
SCL
ALERT
UV
DD
4
2
C
V
DD
INTV
2
0.010Ω
R
19
CC
S
cleared and the control registers are set or cleared as
described in the register section.
After the power-on-reset pulse, the LTC4260 will go
through the following turn-on sequence. First, the UV and
OV pins must indicate that the input power is within the
acceptable range and the BD_PRST pin must be pulled
low. All of these conditions must be satisfied for duration
of 100ms to ensure that any contact bounce during
insertion has ended.
When these initial conditions are satisfied, the ON pin is
checked. If it is high, the external switch turns on. If it is low,
the external switch turns on when the ON pin is brought high
or if a serial bus turn-on command is received.
The switch is turned on by charging up the GATE with a
18µA current source (Figure 2). The voltage at the GATE
pin rises with a slope equal to 18µA/C1 and the supply
inrush current is set at:
When the GATE voltage reaches the FET threshold voltage,
the switch begins to turn on and the SOURCE voltage
follows the GATE voltage as it increases.
SENSE
C3
0.1µF
ADR0 ADR1
LTC4260GN
1
I
15
10Ω
INRUSH
FDB3632
R5
GATE
NC
Q1
16
6.8nF
24
100k
ADR2 GND
C1
R6
=
17
C
C
BD_PRST
SOURCE
L
1
6
TIMER
•
ADIN
GPIO
23
18
FB
µ
18
13
20
14
12
A
4260 F01
C
68nF
T
R7
43.5k
1%
R8
3.57k
1%
R4
100k
+
LTC4260
C
330µF
L
V
48V
OUT
11
4260fa