LTC4259ACGW-1 Linear Technology, LTC4259ACGW-1 Datasheet - Page 11

• Manufacturer Part Number: LTC4259ACGW-1
• Description: IC,Power Control/Management,CMOS,SOP,36PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4259ACGW-1

• Linear Misc Type: Negative Voltage
• Family Name: LTC4259A
• Package Type: SSOP
• Operating Supply Voltage (min): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / Rohs Status: Not Compliant

REGISTER FU CTIO S
Interrupt Registers
Interrupt (Address 00h): Interrupt Register, Read Only. A
transition to logical 1 of any bit in this register will assert
the INT pin (Pin 3) if the corresponding bit in the Int Mask
register is set. Each bit is the logical OR of the correspond-
ing bits in the Event registers. The Interrupt register is Read
Only and its bits cannot be cleared directly. To clear a bit
in the Interrupt register, clear the corresponding bits in the
appropriate Status or Event registers or set bit 7 in the Reset
Pushbutton register (1Ah).
Int Mask (Address 01h): Interrupt Mask, Read/Write. A logic
1 in any bit of the Int Mask register allows the correspond-
ing Interrupt register bit to assert the INT pin if it is set. A
logic 0 in any bit of the Int Mask register prevents the cor-
responding Interrupt bit from affecting the INT pin. The
actual Interrupt register bits are unaffected by the state of
the Int Mask register.
Event Registers
Power Event (Address 02h): Power Event Register, Read
Only. The lower four bits in this register indicate that the
corresponding port Power Enable status bit has changed;
the logical OR of these four bits appears in the Interrupt
register as the Pwr Enable Event bit. The upper four bits
indicate that the corresponding port Power Good status bit
has changed; the logical OR of these four bits appears in
the Interrupt register as the Pwr Good Event bit. The Power
Event bits latch high and will remain high until cleared by
reading from address 03h.
Power Event CoR (Address 03h): Power Event Register,
Clear on Read. Read this address to clear the Power Event
register. Address 03h returns the same data as address 02h
and reading address 03h clears all bits at both addresses.
Detect Event (Address 04h): Detect Event Register, Read
Only. The lower four bits in this register indicate that at least
one detection cycle for the corresponding port has com-
pleted; the logical OR of these four bits appears in the In-
terrupt register as the Detect Complete bit. The upper four
bits indicate that at least one classification cycle for the
corresponding port has completed; the logical OR of these
four bits appears in the Interrupt register as the Class Com-
plete bit. In Manual mode, this register indicates that the
requested detection/classification cycle has completed and
U
U
the LTC4259A-1 is awaiting further instructions. In
Semiauto or Auto modes, these bits indicate that the De-
tect Status and Class Status bits in the Port Status regis-
ters are valid. The Detect Event bits latch high and will remain
high until cleared by reading from address 05h.
Detect Event CoR (Address 05h): Detect Event Register,
Clear on Read. Read this address to clear the Detect Event
register. Address 05h returns the same data as address 04h,
and reading address 05h clears all bits at both addresses.
Fault Event (Address 06h): Fault Event Register, Read Only.
The lower four bits in this register indicate that a
t
cal OR of these four bits appears in the Interrupt register
as the t
connect event has occurred at the corresponding port; the
logical OR of these four bits appears in the Interrupt reg-
ister as the Disconnect bit. The Fault Event bits latch high
and will remain high until cleared by reading from address
07h.
Fault Event CoR (Address 07h): Fault Event Register, Clear
on Read. Read this address to clear the Fault Event regis-
ter. Address 07h returns the same data as address 06h and
reading address 07h clears all bits at both addresses.
t
Only. The lower four bits in this register indicate that a t
fault has occurred at the corresponding port; the logical OR
of these four bits appears in the Interrupt register as the
t
remain high until cleared by reading from address 09h. The
upper four bits in this register are reserved and will always
read as 0.
t
Clear on Read. Read this address to clear the Fault Event
register. Address 09h returns the same data as address 08h
and reading address 09h clears all bits at both addresses.
Supply Event (Address 0Ah): Supply Event Register, Read
Only. Bit 1, Osc Fail, sets when the signal at Pin 36, OSCIN,
is absent or does not have the required amplitude and AC
disconnect cannot operate properly. The Osc Fail bit latches
high and will remain high until cleared by reading at 0Bh.
The Osc Fail bit is set after power on or reset unless the V
supply is not present. Power is removed on ports with AC
ICUT
START
START
START
fault has occurred at the corresponding port; the logi-
ICUT
Event (Address 08h): t
Fault bit. The t
Event CoR (Address 09h): t
Fault bit. The upper four bits indicate that a Dis-
START
Event bits latch high and will
START
LTC4259A-1
START
Event Register, Read
Event Register,
11
4259a1fa
START
EE