LT1952IGN Linear Technology, LT1952IGN Datasheet - Page 10

• Manufacturer Part Number: LT1952IGN
• Description: IC,SMPS CONTROLLER,CURRENT-MODE,SOP,16PIN,PLASTIC
• Manufacturer: Linear Technology

OPERATIO
LT1952/LT1952-1
Introduction
The LT1952/LT1952-1 are current mode synchronous
PWM controllers optimized for control of the simplest
forward converter topology — using only one primary
MOSFET. The LT1952/LT1952-1 are ideal for 25W to
500W power systems where very high efficiency and
reliability, low complexity and cost are required in a small
space. Key features of the LT1952/LT1952-1 include an
adaptive maximum duty cycle clamp for the single primary
MOSFET. An additional output signal is included for syn-
chronous rectifier control. A precision 107mV threshold
senses over-current conditions and triggers Soft-Start for
low stress short circuit protection and control. The key
functions of the LT1952/LT1952-1 are shown in the Block
Diagram in Figure 2.
Part Startup
In normal operation the SD_V
and the V
allow the part to turn on. This combination of pin voltages
allows the 2.5V V
LT1952/LT1952-1 control circuitry and providing up to
2.5mA external drive. SD_V
externally programming an undervoltage lockout (UVLO)
threshold on the system input voltage. Hysteresis on the
UVLO threshold can also be programmed since the
SD_V
after part turn on.
With the LT1952/LT1952-1 turned on, the V
as low as 8.75V (6.5V LT1952-1) before part shutdown
occurs. This V
LT1952-1) combined with low 460µA (400µA LT1952-1)
start-up input current allows low power start-up using a
resistor/capacitor network from system V
V
prevent V
auxiliary winding in the converter takes over supply to the
V
Output Drivers
The LT1952/LT1952-1 have two outputs, SOUT and OUT.
The OUT pin provides a ±1A peak MOSFET gate drive
clamped to 13V. The SOUT pin has a ±50mA peak drive
10
IN
IN
pin.
pin (Figure 3). The V
SEC
IN
pin draws 11µA just before part turn on and 0µA
IN
pin must exceed 14.25V (7.75V LT1952-1) to
falling below its turn off threshold before an
IN
REF
U
pin hysteresis (5.5V LT1952; 1.25V
pin to become active, supplying the
IN
SEC
capacitor value is chosen to
SEC
threshold can be used for
pin must exceed 1.32V
IN
IN
to supply the
pin can drop
clamped to 12V and provides sync signal timing for
synchronous rectification control.
For SOUT and OUT turn on, a PWM latch is set at the start
of each main oscillator cycle. OUT turn on is delayed from
SOUT turn on by a time t
programmed using a resistor from the DELAY pin to
ground and is used to set the timing control of the
secondary synchronous rectifiers for optimum efficiency.
SOUT and OUT turn off at the same time each cycle by one
of three methods:
(1) MOSFET peak current sense at I
(2) Adaptive maximum duty cycle clamp reached during
(3) Maximum duty cycle reset of the PWM latch
During any of the following conditions — low V
SD_V
soft-start event is latched and both SOUT and OUT turn off
immediately (Figure 1).
Leading Edge Blanking
To prevent MOSFET switching noise causing premature
turn off of SOUT or OUT, programmable leading edge
blanking exists. This means both the current sense com-
parator and over-current comparator outputs are ignored
during MOSFET turn on and for an extended period after
the OUT leading edge (Figure 6). The extended blanking
period is programmable by adjusting a resistor from the
BLANK pin to ground.
Adaptive Maximum Duty Cycle Clamp
(Volt-Second Clamp)
For forward converter applications using the simplest
topology of a single MOSFET on the primary, a maximum
switch duty cycle clamp which adapts to transformer input
voltage is necessary for reliable control of the MOSFET.
This volt-second clamp provides a safeguard for trans-
former reset that prevents transformer saturation. Instan-
taneous load changes can cause the converter loop to
demand maximum duty cycle. If the maximum duty cycle
of the switch is too great, the transformer reset voltage can
exceed the voltage rating of the primary-side MOSFET with
load/line transients
SEC
or over-current detection at the OC pin — a
DELAY
(Figure 2). t
SENSE
pin
DELAY
IN
, low
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is