LT1952IGN Linear Technology, LT1952IGN Datasheet - Page 23

• Manufacturer Part Number: LT1952IGN
• Description: IC,SMPS CONTROLLER,CURRENT-MODE,SOP,16PIN,PLASTIC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
Bus Converter: Optimum Output Voltage Tolerance
The Bus Converter applications shown on page 1 and in
Figure 16, provide semi-regulated isolated outputs with-
out the need for an optocoupler, optocoupler driver, refer-
ence or feedback network. The LT1952 Volt-Second clamp
adjusts switch duty cycle inversely proportional to input
voltage to provide an output voltage that is regulated against
input line variations. Some bus converters use a switch
duty cycle limit which causes output voltage variation of
typically ±33% over a 2:1 input voltage range. The LT1952
typically provides a ±10% output variation for the same
input variation. Typical output tolerance is further improved
for the LT1952 by inserting a resistor from the system
input voltage to the SS_MAXDC pin (Rx in Figure 19).
The LT1952 electrical specifications for the OUT Max Duty
Cycle Clamp show typical switch duty cycle to move from
72% to 33% for a 2x change of input voltage
(SS_MAXDC pin = 1.84V). Since output voltage regulation
follows V
72% to 36% (for a 2x input voltage change) provides
minimal output voltage variation for the LT1952 bus con-
verter. To achieve this, an SS_MAXDC pin voltage increase
of 1.09x (36/33) would be required at high input line. A
resistor Rx inserted between the SS_MAXDC pin and sys-
tem input voltage (Figure 19) increases SS_MAXDC volt-
age as input voltage increases, minimizing output voltage
variation over a 2:1 input voltage change.
The following steps determine values for Rx, R
(1) Program switch duty cycle at minimum system input
(a) R
Figure 19. Optimal Programming of Maximum Duty Cycle Clamp
voltage (V
start pull-down)
T(1)
= 10k (minimum allowed to still guarantee soft-
IN
for Bus Converter Applications (Adding Rx)
CLAMP ADJUST INPUT
VOLT-SECOND
CLAMP INPUT
• Duty Cycle, a switch duty cycle change of
S(MIN)
VOLT-SECOND
U
)
INPUT VOLTAGE
SYSTEM
U
R1
R2
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However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Rx
R
B
R
T
W
SD_V
SS_MAXDC
V
REF
LT1952
SEC
1952 F19
U
T
and R
B
(b) Select switch duty cycle for the Bus Converter for a
(c) Calculate R
(2) Calculate Rx
(3) The addition of Rx causes an increase in the original
(a) SS2 = SS1 – [(V
(b) R
(4) The thevinin resistance R
Example:
For a Bus Converter running from 36V to 72V input,
V
choose R
duty cycle at V
S(MIN)
R
R
SS_MAXDC correction = 36%/33% = 1.09
Rx = [(72V – 36V)/(1.84 • 0.09)] • 7.4k = 1.6M
SS2 = 1.84 – [(36V – 1.84) • 7.4k/1.6M] = 1.682V
R
R
R
R
R
given output voltage at V
SS_MAXDC voltage (SS1) (See Applications Informa-
tion “Programming Maximum Duty Cycle Clamp”)
Rx = ([V
R
cycle (V
programmed SS_MAXDC voltage SS1. A new value
for R
SS_MAXDC voltage (SS2) to correct for this offset.
should be re-established for R
(a) R
(b) R
where R
B(1)
THEV(1)
B(2)
THEV(2)
THEV(1)
B
T
THEV(1)
B(2)
(final value) = 20.6k • 1.104 = 22.7k (choose 22.6k)
(final value) = 10k • 1.104 = 11k
= 36V, V
= [1.84V/(2.5V – 1.84V)] • 10k = 28k
= [1.682/(2.5 – 1.682)] • 10k = 20.6k
B
T
B(1)
= [SS2/(2.5 – SS2)] • R
T(1)
(final value) = R
(final value) = R
/R
= [28k • 10k/(28k + 10k)] = 7.4k
= [20.6k • 10k/(20.6k + 10k)] = 6.7k
S(MAX)
THEV(2)
S(MAX) –
= R
= 10k, SS_MAXDC = SS1 = 1.84V (for 72%
THEV(2)
should be calculated to provide a lower
S(MIN)
B(1)
B(1)
S(MAX)
)/actual duty cycle (V
= [SS1/(2.5 – SS1)] • R
= R
S(MIN)
• R
V
= 7.4k/6.7k = 1.104
= 36V)
S(MIN)
B(2)
T(1)
= 72V.
– SS1) • R
B(2)
T(1)
/(R
• R
]/[SS1 • (X – 1)]) • R
THEV(1)
B(1)
T(1)
• (R
• (R
T(1)
S(MIN)
/(R
+ R
T
THEV(1)
THEV(1)
and R
used to calculate Rx
B(2)
THEV(1)
T(1)
S(MAX)
), X = ideal duty
+ R
/R
and calculate
/R
B
LT1952
.
T(1)
THEV(2)
THEV(2)
/Rx]
T(1)
)
)
THEV(1)
23
)
)
1952f