BF1204 T/R NXP Semiconductors, BF1204 T/R Datasheet
BF1204 T/R
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BF1204 T/R Summary of contents
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DATA SHEET handbook, halfpage BF1204 Dual N-channel dual gate MOS-FET Product specification Supersedes data of 2001 Apr 25 DISCRETE SEMICONDUCTORS MBD128 2010 Sep 16 ...
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... NXP Semiconductors Dual N-channel dual gate MOS-FET FEATURES Two low noise gain controlled amplifiers in a single package Superior cross-modulation performance during AGC High forward transfer admittance High forward transfer admittance to input capacitance ratio. APPLICATIONS Gain controlled low noise amplifiers for VHF and UHF ...
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... NXP Semiconductors Dual N-channel dual gate MOS-FET LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER Per MOS-FET; unless otherwise specified V drain-source voltage DS I drain current (DC gate 1 current G1 I gate 2 current G2 P total power dissipation tot T storage temperature ...
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... NXP Semiconductors Dual N-channel dual gate MOS-FET STATIC CHARACTERISTICS = 25 C; per MOS-FET; unless otherwise specified SYMBOL PARAMETER V drain-source breakdown voltage V (BR)DSS V gate-source breakdown voltage (BR)G1-SS V gate-source breakdown voltage (BR)G2-SS V forward source-gate voltage (F)S-G1 V forward source-gate voltage (F)S-G2 V gate-source threshold voltage G1-S(th) ...
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... NXP Semiconductors Dual N-channel dual gate MOS-FET ALL GRAPHS FOR ONE MOS-FET 20 handbook, halfpage V G2 (mA) 3 0.4 0 Fig.3 Transfer characteristics; typical values. 100 handbook, halfpage V G2 (μ 0 Fig.5 Gate 1 current as a function of gate 1 voltage; typical values. 2010 Sep 16 ...
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... NXP Semiconductors Dual N-channel dual gate MOS-FET 20 handbook, halfpage I D (mA G2 Fig.7 Drain current as a function of gate 1 current; typical values. 20 handbook, halfpage I D (mA G2 connected see Fig.19 Fig.9 Drain current as a function of gate and drain supply voltage; typical values. 2010 Sep 16 ...
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... NXP Semiconductors Dual N-channel dual gate MOS-FET 40 handbook, halfpage I G1 (μ 120 k (connected see Fig.19 Fig.11 Gate 1 current as a function of gate 2 voltage; typical values. 120 handbook, halfpage V unw (dBμV) 110 100 120 k MHz MHz; T unw amb Fig.13 Unwanted voltage for 1% cross-modulation as a function of gain reduction ...
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... NXP Semiconductors Dual N-channel dual gate MOS-FET 2 10 handbook, halfpage Y is (mS − Fig.15 Input admittance as a function of frequency; typical values handbook, halfpage y fs (mS ϕ Fig.17 Forward transfer admittance and phase as a function of frequency; typical values. 2010 Sep 16 MLD429 handbook, halfpage b is ...
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... NXP Semiconductors Dual N-channel dual gate MOS-FET handbook, full pagewidth R GEN 50 Ω Fig.19 Cross-modulation test set-up (for one MOS-FET). Scattering parameters mA G2 MAGNITUDE ANGLE (MHz) (ratio) (deg) 3.29 50 0.991 7.12 100 0.987 14.21 200 0.981 21.22 300 0.969 28.14 400 0.958 ...
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... NXP Semiconductors Dual N-channel dual gate MOS-FET PACKAGE OUTLINE Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 1.1 0.30 0.25 mm 0.1 0.20 0.8 0.10 OUTLINE VERSION IEC SOT363 2010 Sep scale 2.2 1.35 2.2 1.3 ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for the marking codes and the package outline drawings which were updated to the latest version. ...