N40P112 austriamicrosystems, N40P112 Datasheet - Page 19

• Manufacturer Part Number: N40P112
• Description: SW NAV JOYSTICK MOD CONTACTLESS
• Manufacturer: austriamicrosystems
• Series: EasyPoint™r
• Type: Navigation Switch, PCB Mountr

Specifications of N40P112

• Output: Contactless Magnetic Switch
• Switch Function: 2 Axis with Select
• Actuator Type: Joystick
• Termination Style: SMD (SMT) Tab
• Operating Force: 35/180gf
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Contact Rating @ Voltage: -

EasyPoint
Datasheet - I ² C i n t e r f a c e
Figure 11. Data Read (Write Pointer, Then Read) - Slave Receive and Transmit
Depending upon the state of the R/W bit, two types of data transfer are possible:
The N40P112 can operate in the following two modes:
Figure 12. Data Write - Slave Receiver Mode
www.austriamicrosystems.com/N40P112
Data transfer from a master transmitter to a slave receiver: The first byte transmitted by the master is the slave address, followed by R/
W = 0. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. If the slave does not understand
the command or data it sends a “not acknowledge”. Data is transferred with the most significant bit (MSB) first.
Data transfer from a slave transmitter to a master receiver: The master transmits the first byte (the slave address). The slave then
returns an acknowledge bit, followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all
received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates
all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with
the most significant bit (MSB) first.
Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. Each byte is followed by an acknowledge
bit (or by a not acknowledge depending on the address-pointer pointing to a valid position). START and STOP conditions are recognized as
the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction
bit
N40P112 address, which is stored in the OTP memory.
The 7-bit slave address is followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte the
device outputs an acknowledge on the SDA. After the N40P112 acknowledges the slave address + write bit, the master transmits a register
address to the N40P112. This sets the address pointer on the N40P112. If the address is a valid readable address the N40P112 answers by
sending an acknowledge. If the address-pointer points to an invalid position a “not acknowledge” is sent. The master may then transmit zero
or more bytes of data. In case of the address pointer pointing to an invalid address the received data are not stored. The address pointer will
increment after each byte transferred independent from the address being valid. If the address-pointer reaches a valid position again, the
N40P112 answers with an acknowledge and stores the data. The master generates a STOP condition to terminate the data write.
S – Start
A – Acknowledge (ACK)
P – Stop
S
(see Figure
<Slave address>
TM
SDA
SCL
1000000
N40P112
Condition
Start
12). The slave address byte is the first byte received after the START condition. The slave address byte contains the 7-bit
0
MSB
1
A
<Word address (n)>
Slave Address
2
XXXXXXXX
6
A
LSB
7
R/W
XXXXXXXX
<Data(n)>
8
Revision 1.1
ACK
9
Data transferred: X+1 Bytes + Acknowledge
Repeated if more Bytes are transferred
A
1
<Data(n+1)>
XXXXXXXX
7
8
A
ACK
9
Repeated Start Condition
Stop Condition or
<Data(n+X)>
XXXXXXXX
NA
P
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