LMP92001SQE/NOPB National Semiconductor, LMP92001SQE/NOPB Datasheet - Page 31

• Manufacturer Part Number: LMP92001SQE/NOPB
• Description: IC ANALOG MONITOR/CTLR 54LLP
• Manufacturer: National Semiconductor

Specifications of LMP92001SQE/NOPB

• Applications: General Purpose
• Current - Supply: 4mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 54-WFQFN Exposed Pad
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Operating Temperature (max): 125C
• Package Type: LLP EP
• Rad Hardened: No
• Supply Voltage Range: 4.75V To 5.5V
• Operating Temperature Range: -40°C To +125°C
• Digital Ic Case Style: LLP
• No. Of Pins: 54
• Peak Reflow Compatible (260 C): Yes
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMP92001SQE/NOPBTR

16.6.3 Block Access
Block Access functionality minimizes overhead in bus trans-
fers involving larger data sets (more than 2 bytes). Internal
register addresses 0xF0 through 0xF5 are interpreted by the
interface as block commands. Accessing any of these ad-
dresses initiates a multi-byte transfer which can be as long as
34 data bytes. The byte length of the transfer is dictated by
the block command itself. Examples of access to internal reg-
ister at address 0xF0 is shown in
BLK0 command is issued meaning that all DACx registers
accessed are accessed sequentially.
16.6.4 I
In cases where Master and Slave interfaces fall out of syn-
chronization there are 2 processes which can reset the Slave
and return it to a known state:
•
TIMEOUT: The device will automatically reset its interface
and wait for a new START condition (by the Master) if SCL
is driven LOW for duration longer than t
Characteristics Table), or SDA is driven LOW by this
2
C-Compatible Bus Reset
Figure 13
FIGURE 14. Block Command WRITE Access
FIGURE 13. Block Command READ Access
OUT
and
(see Electrical
Figure
14.
31
The transfer will consist of 24 bytes – 2 bytes per DACx reg-
ister.
The data WRITE transfers that terminate prematurely will re-
sult in update of registers whose 16-bit words were received
completely. For example, if BLK0 WRITE access is attempt-
ed, and the transfer is terminated after 3 bytes, only DAC1
register will be updated.
•
device for duration longer than t
feature can be disabled by the user, see CGEN register
functionality.
When SDA is in HIGH state, the Master can issue START
condition at any time. The START condition resets the
Slave interface, and Slave expects to see Interface
Address byte next.
30132726
OUT
30132720
. The TIMEOUT
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