LMP92001SQE/NOPB National Semiconductor, LMP92001SQE/NOPB Datasheet
LMP92001SQE/NOPB
Specifications of LMP92001SQE/NOPB
Related parts for LMP92001SQE/NOPB
LMP92001SQE/NOPB Summary of contents
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... No Missing Codes ■ Total Unadjusted Error (TUE) ±0.1% ■ Single-Shot or Continuous Conversion Modes 4.0 Block Diagram National Semiconductor® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation LMP92001 ■ Programmable window comparator function ■ Interrupt signal generation for input out-of-bound condition 12 Programmable Analog Voltage Outputs ■ ...
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Typical Application www.national.com 2 30132706 ...
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Overview The LMP92001 has a flexible, feature-rich functionality which makes it ideally suited for many analog monitoring and control applications, for example base-station PA subsystems. This device provides the analog interface between a pro- grammable supervisor, such as a ...
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Connection Diagram www.national.com LLP-54 (SQA54AB) Top View 4 30132708 ...
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Pin Descriptions Name Pin VDD 14, 50 GND 4, 13, 41, 45 IN1 5 IN2 6 IN3 7 IN4 8 IN5 9 IN6 10 IN7 11 IN8 12 IN9 40 IN10 39 IN11 38 IN12 37 IN13 36 IN14 ...
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Name Pin C[1:4] 27:30 GPIO[0:7] 15:22 INT[1:2] 25:26 AREF 49 DREF 51 9.0 Ordering Information Order Number LMP92001SQE LMP92001SQX www.national.com ESD Structures NS Package Number SQA54AB SQA54AB 6 Function Asynchronous DAC output control digital inputs Digital I/O. CMOS Input or ...
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General Description ......................................................................................................................... 1 2.0 Features ........................................................................................................................................ 1 3.0 Applications .................................................................................................................................... 1 4.0 Block Diagram ................................................................................................................................ 1 5.0 Typical Application ........................................................................................................................... 2 6.0 Overview ........................................................................................................................................ 3 6.1 17-CHANNEL ANALOG SENSE WITH 12-BIT ADC ...................................................................... 3 6.2 PROGRAMMABLE ANALOG CONTROL ...
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GENERAL PURPOSE I/O ..................................................................................................... 28 16.6 SERIAL INTERFACE ............................................................................................................ 28 16.6 C-Compatible Protocol .............................................................................................. 29 16.6.2 Device Address .......................................................................................................... 30 16.6.3 Block Access ............................................................................................................. 31 16.6 C-Compatible Bus Reset ........................................................................................... 31 17.0 Application Circuit Example ...
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... Absolute Maximum Ratings 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD Relative to GND Voltage between any 2 pins(Note 3) Current in or out of any pin (Note 3) Current through VDD or GND Junction Temperature ...
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Symbol Parameter ZCO Zero Code Output FSO Full Scale Output at code 4095 Output Short Circuit Current I OS (Source) (Note 5) Output Short Circuit Current I OS (Sink) (Note 5) Continuous Output Current per I O Channel (to prevent ...
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Symbol Parameter DIGITAL INPUT CHARACTERISTICS (SDA and SCL) V Input HIGH Voltage IH V Input LOW Voltage IL Hysteresis I Digital Input Current IND C Input Capacitance IND DIGITAL OUTPUT CHARACTERISTICS (INT and GPIO) V Output LOW Voltage OL V ...
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Note 1: Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond ...
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Typical Performance Characteristics ADC: DNL VDD = 5V, AREF = 4.5V, T CREF.AEXT = 1, Single Channel Continuous Mode 1024 CODE DAC: DNL VDD = 5V, DREF = 4.5V, T CREF.DEXT = 1, ...
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ADC: DNL vs. Temperature VDD = 5V, AREF = 4.5V, CREF.AEXT = 1 2 Minimum DNL Maximum DNL -50 - TEMPERATURE (°C) DAC: DNL vs Temperature VDD = 5V, DREF = 4.5V, CREF.DEXT = ...
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Internal Reference Output Temperature Drift VDD = 5V, CREF.AEXT = 0, CREF.DEXT = 0 4.505 AREF DREF 4.504 4.503 4.502 4.501 4.500 4.499 4.498 4.497 4.496 4.495 -50 - 100 125 TEMPERATURE (°C) 30132759 15 www.national.com ...
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Register Set RESERVED registers in the map in TER MAP should not be accessed for either read or write operations as this may lead to unpredictable behavior of the device. 15.1 REGISTER MAP Addr. Name 0x00 0x01 TEST 0x02 ...
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Addr. Name 0x43 LIH9 0x44 LIH10 0x45 LIH11 0x46 LIL1 0x47 LIL2 0x48 LIL3 0x49 LIL9 0x4A LIL10 0x4B LIL11 0x66 CREF 0x80 DAC1 0x81 DAC2 0x82 DAC3 0x83 DAC4 0x84 DAC5 0x85 DAC6 0x86 DAC7 0x87 DAC8 0x88 DAC9 ...
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STATUS REGISTERS 15.3.1 General Status Register: SGEN[7:0], default = 0x40 Bx Name Function 7 BUSY 1 - while ADC is converting 6 RDYN 0 - when power up completed 5:3 - RESERVED any bit ...
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CONTROL REGISTERS 15.4.1 General Configuration Register: CGEN[7:0], default = 0x00 Bx Name Function 1 - RESETS all registers and self to 7 RST POR value 6:3 - RESERVED 1 - disable I 2 C-compatible TIMEOUT. 2 TOD See Section ...
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ADC One-Shot Conversion Trigger Register : CTRIG[7:0], default = 0x00 Bx Name Function 7:1 - RESERVED Writing any value, when CGEN.STRT=0, will trigger Single-Shot conversion. The 0 SNGL CGEN.LCK bit must be set for the conversion sequence to begin. ...
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BLOCK COMMANDS Block access functionality is discussed in Block Access. Block Start Block End Name Address Address BLK0 0x80 BLK1 0x86 BLK2 0x20 BLK3 0x28 BLK4 0x40 BLK5 0x46 Section 16.6.3 Block Length in Bytes 0x8B 24 Single command ...
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Application Information 16.1 ANALOG SENSE SUBSYSTEM The device is capable of monitoring externally ap- plied voltages and an internal analog temperature sensor. The system is centered around 12-bit SAR ADC fronted by a 17-input mux. Results ...
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FIGURE 2. ADC Finite State Machine Diagram 23 30132710 www.national.com ...
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Reference By default the ADC operates from the external reference volt- age applied at AREF pin of the device. Due to the architecture of the ADC the DC current flowing into the AREF input is zero during conversion. However, ...
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Interrupt Subsystem Device outputs INT1 and INT2 report out of bounds conditions as determined by the digital window comparator. INT1 and INT2 are open collector outputs and are active LO. INT1 re- ports out of bound conditions at ADC ...
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Typical DAC core output VOUTx as a function of the DACx input , x=1...12, can be expressed as: 16.2.2 Reference By default the DACs operate from the external reference volt- age applied at the DREF pin of the device. Given ...
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Note that CDAC.OFF affects all OUTx, whereas Cy affects only channels assigned to it. The correspondence between Device Pin 16.3 TEMPERATURE SENSOR The output voltage of the analog temperature sensor can be sampled via ADC ...
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GENERAL PURPOSE I/O The GPIO[7:0] port is memory mapped to registers SGPI and CGPO. Both registers are accessible through the I patible interface. The SGPI register content reflects at all times the digital state at the GPIOx device pins. ...
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I 2 C-Compatible Protocol Two wires, SCL and SDA, are used to carry data between master (the digital supervisor), and a slave (LMP92001). Mas- ter generates a START condition which commences all data transfers. And only the master generates ...
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Device Address Interface Address of the device can be set via 2 pins: AS0 and AS1. Each address setting pin recognizes 3 levels: Device Pins AS1 AS0 LOW LOW LOW MID LOW HIGH MID LOW MID MID MID HIGH ...
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Block Access Block Access functionality minimizes overhead in bus trans- fers involving larger data sets (more than 2 bytes). Internal register addresses 0xF0 through 0xF5 are interpreted by the interface as block commands. Accessing any of these ad- dresses ...
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Application Circuit Example www.national.com 32 30132742 ...
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Physical Dimensions inches (millimeters) unless otherwise noted LLP-54 Package NS Package Number SQA54A 33 www.national.com ...
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