KSZ8842-PMBL AM TR Micrel Inc, KSZ8842-PMBL AM TR Datasheet - Page 51

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KSZ8842-PMBL AM TR

Manufacturer Part Number
KSZ8842-PMBL AM TR
Description
2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface( )
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8842-PMBL AM TR

Number Of Primary Switch Ports
2
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.5V
Operating Supply Voltage (min)
3.1V
Operating Temperature Classification
Industrial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Supplier Unconfirmed
Micrel, Inc.
respond to when receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB,
where the bytes are received from left to right, and the bits within each byte are received right to left (LSB to MSB). The
actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101.
The following table shows the register bit fields.
Reserved (Offset 0x0206 - 0x020A
The following table shows the register bit fields.
On-Chip Bus Control Register (Offset 0x0210): OBCR
This register controls the on-chip bus speed for the KSZ8842-PMQL/PMBL. It is used for reduced power consumption
when the external host CPU is running at a slow frequency. The default of the on-chip bus speed is 25MHz. When the
external host CPU is running at a higher clock rate, adjust the on-chip bus for the best performance.
The following table shows the register bit fields.
EEPROM Control Register (Offset 0x0212): EEPCR
KSZ8842-PMQL/PMBL supports designs with and without an EEPROM system design. To support an external
EEPROM, tie the EEPROM Enable (EEEN) pin/ball to High; otherwise, tie it to Low or no connect. The KSZ8842-
PMQL/PMBL allows software to access (read and write) the EEPROM directly; that is, the EEPROM access timing can
be fully controlled by the software if the EEPROM Software Access bit 4 in EEPCR is set.
The following table shows the register bit fields.
October 2007
15 – 0
15 – 2
15 – 5
1 – 0
15-0
Bit
Bit
Bit
Bit
4
3
2
1
0
Default
Default
Default
Default
0x0000
0x3
00
00
00
00
0
0
R/W
R/W
R/W
R/W
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
Description
MARH MAC Address High
The Most significant word of the MAC address
Description
Reserved
Description
Reserved
OBSC On-Chip Bus Speed Control
00: 125MHz
01: 62.5MHz
10: 41.66MHz
11: 25MHz
Description
Reserved
EESA EEPROM Software Access
1 = Enable software to access EEPROM through bit 3 to bit 0.
0 = Disable software to access EEPROM.
EECB EEPROM Status Bits
Bit 3: Data Out from EEPROM. This bit directly reflects the value of the
EEDI pin/ball.
EECB EEPROM Control Bits
Bit 2: Data In to EEPROM. This bit directly controls the device’s the EEDO
pin/ball.
EECB EEPROM Control Bits
Bit 1: Serial Clock. This bit directly controls the device’s the EESK pin/ball.
EECB EEPROM Control Bits
Bit 0: Chip Select. This bit directly controls the device’s the EECS pin/ball.
51
KSZ8842-PMQL/PMBL
M9999-100207-1.5

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