KSZ8842-PMBL AM TR Micrel Inc, KSZ8842-PMBL AM TR Datasheet - Page 49

• Manufacturer Part Number: KSZ8842-PMBL AM TR
• Description: 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-PMBL AM TR

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Micrel, Inc.
MAC Additional Station Address Low Register (MAAL0-15)
The KSZ8842-PMQL/PMBL supports 16 additional MAC addresses for MAC address filtering. This MAC address is
used to define one of the 16 destination addresses that the KSZ8842-PMQL/PMBL will respond to when receiving
frames on the port. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are
received left to right, and the bits within each byte are received right to left (LSB to MSB). The actual transmitted and
received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101.
The following table shows the register bit fields.
MAC Additional Station Address High Register (MAAH0-15)
The KSZ8842-PMQL/PMBL supports 16 additional MAC addresses for MAC address filtering. This MAC address is
used to define one of the 16 destination addresses that the KSZ8842-PMQL/PMBL will respond to when receiving
frames on the host port. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes
are received left to right, and the bits within each byte are received right to left (LSB to MSB). The actual transmitted
and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101.
The following table shows the register bit fields.
The following table shows the register map for all 16 additional MAC address registers.
October 2007
30 – 16
31 – 0
15 - 0
Bit
Bit
31
ADD MAC High 0
ADD MAC High 1
ADD MAC High 2
ADD MAC High 3
ADD MAC High 4
ADD MAC High 5
ADD MAC High 6
ADD MAC High 7
ADD MAC High 8
ADD MAC Low 0
ADD MAC Low 1
ADD MAC Low 2
ADD MAC Low 3
ADD MAC Low 4
ADD MAC Low 5
ADD MAC Low 6
ADD MAC Low 7
ADD MAC Low 8
Register
Default
Default
0x0
–
0
–
R/W
R/W
RW
RW
RW
RO
IDENTIFIER
MAAH0
MAAH1
MAAH2
MAAH3
MAAH4
MAAH5
MAAH6
MAAH7
MAAH8
MAAL0
MAAL1
MAAL2
MAAL3
MAAL4
MAAL5
MAAL6
MAAL7
MAAL8
Description
MAAL0 MAC Additional Station Address 0 Low 4 bytes
The least significant word of the additional MAC 0 station address.
Description
MAA0E MAC Additional Station Address 0 Enable
When set, the additional MAC address is enabled for received frames.
When reset, the additional MAC address is disabled.
Reserved
MAAH0 MAC Additional Station Address 0 High 2 bytes
The most significant word of the additional MAC 0 station address.
49
OFFSET
0x00AC
0x00BC
0x008C
0x009C
0x00A0
0x00A4
0x00A8
0x00B0
0x00B4
0x00B8
0x00C0
0x00C4
0x0080
0x0084
0x0088
0x0090
0x0094
0x0098
KSZ8842-PMQL/PMBL
M9999-100207-1.5