KSZ8841-16MVLI Micrel Inc, KSZ8841-16MVLI Datasheet - Page 56

• Manufacturer Part Number: KSZ8841-16MVLI
• Description: Single Ethernet Port + Generic (8, 16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8841-16MVLI

• Controller Type: Ethernet Controller, MAC
• Interface: Bus
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1632 - BOARD EVALUATION KSZ8841-16MVL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-2114; KSZ8841-16MVLI

Bank 3 Memory BIST Info Register (0x04): MBIR
Bank 3 Global Reset Register (0x06): GRR
This register controls the global reset function with information programmed by the CPU.
Bank 3 Power Management Capabilities Register (0x08): PMCR
This register is a read-only register that provides information on the K8841M power management capabilities. These
bits are automatically downloaded from Configparam word of EEPROM , if pin EEEN is high (enabled EEPROM)
October 2007
Micrel, Inc.
Bit
15-13
12
11
10-5
4
3
2-0
Bit
15-1
0
Bit
15
14
13
12
11
Default Value
0
1
0
0
0
0x0
-
-
-
-
-
-
0
Default Value
Default Value
0x0000
R/W
RO
RO
RO
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
R/W
RO
RW
Description
Reserved.
TXMBF TX Memory Bist Finish
When set, it indicates the Memory Built In Self Test completion for the TX Memory.
TXMBFA TX Memory Bist Fail
When set, it indicates the Memory Built In Self Test has failed.
Reserved
RXMBF RX Memory Bist Finish
When set, it indicates the Memory Built In Self Test completion for the RX Memory.
RXMBFA RX Memory Bist Fail
When set, it indicates the Memory Built In Self Test has failed.
Reserved.
Description
Reserved.
Global Soft Reset
= 1 software reset is active.
= 0 software reset is inactive.
Software reset will affect PHY, MAC, QMU, DMA, and the switch core, only the BIU
(base address registers) remains unaffected by a software reset.
Description
PME Support D3 (cold)
This bit defaults to 0, so the KSZ8841M does not support D3(cold)
PME Support D3 (hot)
This bit is 1 only,it is indicating that the KSZ8841M can assert PME event (PMEN pin
14) in D3(hot) power state.(see bit1:0 in PMCS register)
PME Support D2
If this bit is set, the wake-up signals will assert PME event (PMEN pin 14) when the
KSZ8841M is in D2 power state and PME_EN (see bit8 in PMCS register) is set.
Otherwise, the KSZ8841M does not assert PME event (PMEN pin 14) when the
KSZ8841M is in D2 power state.
The value of this bit is loaded from the PME_D2 bit of 0x6 in the serial EEPROM
(without an EEPROM, this bit defaults to 0).
PME Support D1
If this bit is set, the wake-up signals will assert PME event (PMEN pin 14) when the
KSZ8841M is in D1 power state and PME_EN (see bit8 in PMCS register) is set.
Otherwise, the KSZ8841M does not assert PME event (PMEN pin 14) when the
KSZ8841M is in D1 power state.
The value of this bit loaded from the PME_D1 bit of 0x6 in the serial EEPROM (without
an EEPROM, this bit defaults to 0).
PME Support D0
This bit defaults to 0, it is indicating that the KSZ8841M does not assert PME event
56
KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6