FM24C16B-GTR Ramtron, FM24C16B-GTR Datasheet - Page 7

• Manufacturer Part Number: FM24C16B-GTR
• Description: SOIC8 T&R
• Manufacturer: Ramtron

Ramtron
Endurance
The FM24C16B internally operates with a read and
restore mechanism. Therefore, endurance cycles are
applied for each read or write cycle. The memory
architecture is based on an array of rows and
columns. Each read or write access causes an
endurance cycle for an entire row. In the FM24C16B,
a row is 64 bits wide. Every 8-byte boundary marks
19 July 2011
By FM24C16B
By Master
By FM24C16B
By Master
Start
S
By FM24C16B
By Master
Slave Address
Start
S
Slave Address
0
Address
Address
A
Start
S
Word Address
Slave Address
Figure 9. Selective (Random) Read
Acknowledge
Figure 7. Current Address Read
Address
1
Figure 8. Sequential Read
A
Acknowledge
A
Start
S
Acknowledge
Data Byte
1
Slave Address
A
Address
the beginning of a new row. Endurance can be
optimized by ensuring frequently accessed data is
located in different rows. Regardless, FRAM read
and write endurance is effectively unlimited at the
1MHz two-wire speed. Even at 3000 accesses per
second to the same row, 10 years time will elapse
before 1 trillion endurance cycles occur.
Acknowledge
Data Byte
1
Data
A
A
Data
Data Byte
Acknowledge
Data Byte
FM24C16B - 16Kb 5V I2C F-RAM
No
1
Acknowledge
P
Data
A
Acknowledge
No
1 P
Data Byte
Stop
Acknowledge
No
1 P
Stop
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Stop