EVAL-ADF7021-VDB2Z Analog Devices Inc, EVAL-ADF7021-VDB2Z Datasheet - Page 35

• Manufacturer Part Number: EVAL-ADF7021-VDB2Z
• Description: 868 - 870MHz - EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Type: Transceiverr

Specifications of EVAL-ADF7021-VDB2Z

• Frequency: 868MHz ~ 870MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AUTOMATIC SYNC WORD DETECTION (SWD)
The ADF7021-V also supports automatic detection of the sync
or ID fields. To activate this mode, the sync (or ID) word must
be preprogrammed into the ADF7021-V. In receive mode, this
preprogrammed word is compared to the received bit stream.
When a valid match is identified, the external SWD pin is
asserted by the ADF7021-V on the next Rx clock pulse.
This feature can be used to alert the microprocessor that a
valid channel has been detected. It relaxes the computational
requirements of the microprocessor and reduces the overall
power consumption.
The SWD signal can also be used to frame the received packet
by staying high for a preprogrammed number of bytes. The data
packet length can be set in Register 12, Bits[DB15:DB8].
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The SWD pin status can be configured by setting Bits[DB7:DB6]
in Register 12. Bits[DB5:DB4] in Register 11 are used to set the
length of the sync/ID word, which can be 12, 16, 20, or 24 bits
long. A value of 24 bits is recommended to minimize false sync
word detection in the receiver that can occur during recovery of
the remainder of the packet or when a noise/no signal is present
at the receiver input. The transmitter must transmit the sync
byte MSB first, LSB last to ensure proper alignment in the
receiver sync-byte-detection hardware.
An error tolerance parameter can also be programmed that
accepts a valid match when up to three bits of the word are
incorrect. The error tolerance value is assigned in Register 11,
Bits[DB7:DB6].
ADF7021-V