EVAL-ADF7021-VDB2Z Analog Devices Inc, EVAL-ADF7021-VDB2Z Datasheet - Page 29

• Manufacturer Part Number: EVAL-ADF7021-VDB2Z
• Description: 868 - 870MHz - EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Type: Transceiverr

Specifications of EVAL-ADF7021-VDB2Z

• Frequency: 868MHz ~ 870MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset Correction Clock
In Register 3, the user should set the BBOS_CLK_DIVIDE bits
(Bits[DB5:DB4]) to give a baseband offset clock (BBOS CLK)
frequency between 1 MHz and 2 MHz.
where BBOS_CLK_DIVIDE can be set to 4, 8, 16, or 32.
AGC Information and Timing
AGC is selected by default and operates by setting the appro-
priate LNA and filter gain settings for the measured RSSI level.
To enter one of the LNA/mixer modes listed in Table 14, the
user can disable AGC by writing to Register 9. After each gain
change, the AGC loop waits for a programmed time to allow
transients to settle. This AGC update rate is set according to
where:
SEQ_CLK_DIVIDE = 100 kHz (Register 3, Bits[DB25:DB18]).
AGC_CLK_DIVIDE is set by Register 3, Bits[DB31:DB26]. A
value of 33 is recommended.
It is recommended that AGC_CLK_DIVIDE be set to a value of
33, which allows a settling time of 333 μs for each gain change.
By using the recommended setting for AGC_CLK_DIVIDE, the
total AGC settling time is
Table 14. LNA/Mixer Modes (Register 9 Settings)
Receiver Mode
High Sensitivity
Enhanced Linearity,
Medium Gain
Enhanced Linearity,
Low Gain
Enhanced Linearity,
Mode (Default)
High Gain
Medium Gain
Low Gain
BBOS CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE)
AGC Update Rate (Hz) =
AGC
Settling
Time
LNA_MODE
(Bit DB25)
0
0
1
1
1
1
(sec)
=
SEQ
Number
AGC
AGC
_
LNA_GAIN
(Bits[DB21:DB20])
30
30
10
10
3
3
CLK
_
of
Update
CLK
AGC
_
DIVIDE
_
DIVIDE
Gain
Rate
(Hz)
Changes
(Hz)
MIXER_LINEARITY
(Bit DB28)
0
1
0
1
0
1
Rev. 0 | Page 29 of 60
The total AFC settling time depends on the number of AGC
gain changes during reception of a packet. A total of five gain
changes gives a worst-case AGC settling time of 5 × 333 μs. To
allow for AGC settling, the preamble length should be adjusted
accordingly.
RSSI Formula (Converting to dBm)
The RSSI formula is
where:
Readback Code is given by Bit RV7 to Bit RV1 in the readback
register (see Figure 57 and the Readback Format section).
Gain Mode Correction is given by the values in Table 13.
The LNA gain (LG2, LG1) and filter gain (FG2, FG1) values
are also obtained from the readback register, as part of an RSSI
readback.
Table 13. Gain Mode Correction
LNA Gain
(LG2, LG1)
H (1, 0)
M (0, 1)
M (0, 1)
M (0, 1)
L (0, 0)
An additional factor should be introduced to account for losses
in the front-end-matching network/antenna.
Input Power (dBm) = (−130 dBm + (Readback Code +
Gain Mode Correction)) × 0.5
Sensitivity (2FSK,
Data Rate = 4.8 kbps,
f
−116.5
−113
−108
−102
−99
−91
DEV
= 4 kHz) (dBm)
Filter Gain
(FG2, FG1)
H (1, 0)
H (1, 0)
M (0, 1)
L (0, 0)
L (0, 0)
Rx Current
Consumption (mA)
20.1
20.1
17.9
17.9
17.9
17.9
Gain Mode
Correction
0
24
38
58
86
ADF7021-V
Input IP3
(dBm)
−24
−20
−13.5
−9
−5
−3