EVAL-AD7783EBZ Analog Devices Inc, EVAL-AD7783EBZ Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD7783EBZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7783EBZ

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 32k
• Data Interface: SPI™, QSPI™, MICROWIRE™, and DSP
• Inputs Per Adc: 1 Differential
• Input Range: ±2.56 V
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7783
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7783
Input Logic 0 = 0 V, Logic 1 = V
TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
Slave Mode Timing
Master Mode Timing
NOTES
1
2
3
4
5
1
ADC
2
3
4
7
8
9
Sample tested during initial release to ensure compliance. All input signals are specified with t
See Figure 2.
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
SCLK active edge is falling edge of SCLK.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin-
quish times of the part and as such are independent of external bus loading capacitances.
3
5
t
t
t
t
t
5
6
5
6
10
Limit at T
(B Version)
30.5176
50.54
0
60
80
2 ¥ t
0
60
80
10
80
0
10
80
100
100
t
t
t
3t
1
1
1
/2
/2
/2
DD
1
/2
, unless otherwise noted.)
ADC
MIN
Figure 1. Load Circuit for Timing Characterization
1, 2
, T
TO OUTPUT
MAX
(V
DD
PIN
= 2.7 V to 3.6 V or V
50pF
Unit
ms typ
ms typ
ns min
ns max
ns max
ns typ
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns min
ms typ
ms typ
ms min
ms max
–4–
I
I
SINK
SOURCE
DD
(1.6mA WITH V
100 A WITH V
= 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz;
( 200 A WITH V
R
100 A WITH V
Conditions/Comments
Crystal Oscillator Period
19.79 Hz Update Rate
CS Falling Edge to DOUT Active
V
V
Channel Settling Time
SCLK Active Edge to Data Valid Delay
V
V
Bus Relinquish Time after CS Inactive Edge
CS Rising Edge to SCLK Inactive Edge Hold Time
SCLK Inactive to DOUT High
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK Low Pulse Width
DOUT Low to First SCLK Active Edge
= t
DD
DD
DD
DD
1.6V
F
= 5 ns (10% to 90% of V
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
DD
DD
= 5V
= 3V)
DD
DD
= 5V
= 3V)
DD
OL
) and timed from a voltage level of 1.6 V.
or V
OH
limits.
4
4
REV. B