EVAL-AD5272SDZ Analog Devices Inc, EVAL-AD5272SDZ Datasheet - Page 7

• Manufacturer Part Number: EVAL-AD5272SDZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5272SDZ

• Main Purpose: Digital Potentiometer
• Embedded: No
• Utilized Ic / Part: AD5272
• Primary Attributes: 1 Channel, 1024 Position
• Secondary Attributes: 2.7 ~ 5.5 V, 5 ppm/°C, I²C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERFACE TIMING SPECIFICATIONS
V
Table 7.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
SCL
1
2
3
4
5
6
7
8
9
10
11
11A
12
13
SP
EXEC
RDAC_R-PERF
RDAC_NORMAL
MEMORY_READ
MEMORY_PROGRAM
RESET
POWER-UP
Maximum bus capacitance is limited to 400 pF.
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.
Refer to t
Refer to t
Maximum time after V
DD
3
2
4, 5
= 2.5 V to 5.5 V; all specifications T
6
RDAC_R-PERF
MEMORY_READ
and t
and t
Conditions
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
RESET pulse time
Fast mode
DD
RDAC_NORMAL
MEMORY_PROGRAM
− V
SS
is equal to 2.5 V.
for RDAC register write operations.
1
for memory commands operations.
MIN
Min
4
0.6
4.7
1.3
250
100
0
0
4.7
0.6
4
0.6
160
4.7
1.3
4
0.6
20
0
500
Limit at T
to T
MAX
, unless otherwise noted.
MIN
Max
100
400
3.45
0.9
1000
300
300
300
1000
300
1000
300
300
300
50
2
600
6
350
600
2
, T
MAX
Rev. C | Page 7 of 28
Unit
kHz
kHz
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
μs
μs
ns
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
μs
ms
μs
ms
Description
Serial clock frequency
Serial clock frequency
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
after an acknowledge bit
t
after an acknowledge bit
t
t
Minimum RESET low time
Pulse width of spike suppressed
Command execute time
RDAC register write command execute time (R-Perf mode)
RDAC register write command execute time (normal mode)
Memory readback execute time
Memory program time
Reset 50-TP restore time
Power-on 50-TP restore time
HIGH
HIGH
LOW
LOW
SU;DAT
SU;DAT
HD;DAT
HD;DAT
SU;STA
SU;STA
HD;STA
HD;STA
HD;STA
BUF
BUF
SU;STO
SU;STO
RDA
RDA
FDA
FDA
RCL
RCL
RCL1
RCL1
FCL
FCL
, rise time of SCL signal
, rise time of SCL signal
, fall time of SCL signal
, fall time of SCL signal
, bus free time between a stop and a start condition
, bus free time between a stop and a start condition
, rise time of SDA signal
, rise time of SDA signal
, fall time of SDA signal
, fall time of SDA signal
, SCL low time
, SCL low time
, rise time of SCL signal after a repeated start condition and
, rise time of SCL signal after a repeated start condition and
, SCL high time
, SCL high time
, set-up time for a repeated start condition
, set-up time for a repeated start condition
, setup time for a stop condition
, setup time for a stop condition
, data setup time
, data setup time
, hold time (repeated) start condition
, hold time (repeated) start condition
, hold time (repeated) start condition
, data hold time
, data hold time
AD5272/AD5274