EPM7512BFC256-10 Altera, EPM7512BFC256-10 Datasheet - Page 7

• Manufacturer Part Number: EPM7512BFC256-10
• Description: MAX 7000/S/AE/B
• Manufacturer: Altera

Specifications of EPM7512BFC256-10

• Family Name: MAX 7000B
• Memory Type: EEPROM
• # Macrocells: 512
• Number Of Usable Gates: 10000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 32
• # I/os (max): 212
• Operating Supply Voltage (typ): 2.5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / Rohs Status: Not Compliant

Figure 2. MAX 7000B Macrocell
Altera Corporation
36 Signals
from PIA
LAB Local Array
Product Terms
16 Expander
Macrocells
The MAX 7000B macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists of
three functional blocks: the logic array, the product-term select matrix,
and the programmable register.
macrocell.
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
■
■
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
Product-
Select
Matrix
Term
Shared Logic
Expanders
Parallel Logic
Expanders
(from other
macrocells)
MAX 7000B Programmable Logic Device Data Sheet
Global
Clear
Select
Clear
Clocks
2
Global
Figure 2
VCC
Enable
Select
Clock/
shows the MAX 7000B
Fast Input
Select
ENA
D/T
CLRN
PRN
To PIA
Q
Programmable
Register
Register
Bypass
From
I/O pin
To I/O
Control
Block
7