EPM7512BFC256-10 Altera, EPM7512BFC256-10 Datasheet - Page 6

• Manufacturer Part Number: EPM7512BFC256-10
• Description: MAX 7000/S/AE/B
• Manufacturer: Altera

Specifications of EPM7512BFC256-10

• Family Name: MAX 7000B
• Memory Type: EEPROM
• # Macrocells: 512
• Number Of Usable Gates: 10000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 32
• # I/os (max): 212
• Operating Supply Voltage (typ): 2.5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / Rohs Status: Not Compliant

MAX 7000B Programmable Logic Device Data Sheet
Figure 1. MAX 7000B Device Block Diagram
Note:
(1)
6
EPM7032B, EPM7064B, EPM7128B, and EPM7256B devices have six output enables. EPM7512B devices have ten
output enables.
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/GCLK1
INPUT/OE1
2 to 16 I/O
2 to 16 I/O
6 or 10 Output Enables (1)
Control
Control
Block
Block
I/O
I/O
Logic Array Blocks
The MAX 7000B device architecture is based on the linking of
high-performance LABs. LABs consist of 16 macrocell arrays, as shown in
Figure
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
■
■
■
6 or 10
6 or 10
2 to 16
2 to 16
2 to 16
2 to 16
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used for fast
setup times
1. Multiple LABs are linked together via the PIA, a global bus that
LAB A
LAB C
Macrocells
Macrocells
33 to 48
1 to 16
2 to 16
2 to 16
16
16
36
36
PIA
36
36
2 to 16
2 to 16
16
16
Macrocells
Macrocells
17 to 32
49 to 64
LAB D
LAB B
6 or 10 Output Enables (1)
2 to 16
2 to 16
2 to 16
2 to 16
Control
Control
Block
Block
Altera Corporation
I/O
I/O
6 or 10
6 or 10
2 to 16 I/O
2 to 16 I/O