EPM7128SQC160-6 Altera, EPM7128SQC160-6 Datasheet - Page 48

• Manufacturer Part Number: EPM7128SQC160-6
• Description: MAX 7000/S/AE/B
• Manufacturer: Altera

MAX 7000 Programmable Logic Device Family Data Sheet
48
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
f
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
ODH
CNT
CNT
ACNT
ACNT
MAX
Table 34. EPM7256S External Timing Parameters
Input to non-registered output
I/O input to non-registered
output
Global clock setup time
Global clock hold time
Global clock setup time of fast
input
Global clock hold time of fast
input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear
and preset
Output data hold time after
clock
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
Parameter
Tables 34
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(2)
C1 = 35 pF
(4)
(4)
(5)
and
Conditions
35
(3)
show the EPM7256S AC operating conditions.
Note (1)
128.2
128.2
166.7
Min
1.9
3.9
0.0
3.0
0.0
3.0
3.0
0.8
3.0
3.0
3.0
1.0
-7
Max
7.5
7.5
4.7
7.8
7.8
7.8
Speed Grade
100.0
100.0
125.0
Min
7.0
0.0
3.0
0.5
4.0
4.0
2.0
3.0
4.0
4.0
4.0
1.0
-10
Max
10.0
10.0
10.0
10.0
10.0
5.0
100.0
Min
11.0
76.9
76.9
0.0
3.0
0.0
5.0
5.0
4.0
4.0
6.0
6.0
6.0
1.0
Altera Corporation
-15
Max
15.0
15.0
15.0
13.0
13.0
8.0
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns