EPM7128SQC160-6 Altera, EPM7128SQC160-6 Datasheet - Page 46

• Manufacturer Part Number: EPM7128SQC160-6
• Description: MAX 7000/S/AE/B
• Manufacturer: Altera

MAX 7000 Programmable Logic Device Family Data Sheet
46
Symbol
t
t
t
t
t
t
t
t
t
f
t
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
CL
ASU
AH
ACO1
ACH
ACL
CPPW
ODH
CNT
CNT
ACNT
ACNT
MAX
Table 32. EPM7192S External Timing Parameters (Part 2 of 2)
Table 33. EPM7192S Internal Timing Parameters (Part 1 of 2)
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear
and preset
Output data hold time after
clock
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Output buffer and pad delay
Output buffer and pad delay
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Parameter
Parameter
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(2)
C1 = 35 pF
(4)
(4)
(5)
Conditions
Conditions
(6)
(6)
(3)
125.0
125.0
166.7
Min
1.8
3.0
1.0
3.0
3.0
3.0
1.0
Min
-7
-7
Max
7.8
8.0
8.0
Max
Note (1)
0.3
3.2
4.2
1.2
0.9
0.5
4.0
9.0
Note (1)
0.3
3.1
3.1
1.0
5.5
4.5
Speed Grade
100.0
100.0
125.0
Min
4.0
2.0
3.0
4.0
4.0
4.0
1.0
Speed Grade
Min
-10
-10
Max
10.0
10.0
10.0
Max
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
100.0
Min
76.9
76.9
5.0
4.0
4.0
6.0
6.0
6.0
1.0
Min
Altera Corporation
-15
-15
Max
15.0
13.0
13.0
Max
10.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
7.0
6.0
7.0
Unit
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns