EP3C5E144A7N Altera, EP3C5E144A7N Datasheet - Page 88
![Cyclone III](/photos/37/16/371628/144pin_eqfp_sml.jpg)
EP3C5E144A7N
Manufacturer Part Number
EP3C5E144A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet
1.EP3C5E144A7N.pdf
(274 pages)
Specifications of EP3C5E144A7N
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
Lead Free Status / Rohs Status
Compliant
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5–24
PLL Cascading
Figure 5–19. PLL Cascading Using GCLK
PLL Reconfiguration
Cyclone III Device Handbook, Volume 1
Output from PLL
Control Blocks
Five Clock
from two Clock
pins at adjacent
edge of device
Remote clock
CLK[0..3]
Two PLLs are cascaded to each other through the clock network. If your design
cascades PLLs, the source (upstream) PLL must have a low-bandwidth setting, while
the destination (downstream) PLL must have a high-bandwidth setting.
Figure 5–19
PLLs use several divide counters and different VCO phase taps to perform frequency
synthesis and phase shifts. In Cyclone III device family PLLs, you can reconfigure
both counter settings and phase shift the PLL output clock in real time. You can also
change the charge pump and loop filter components, which dynamically affects PLL
bandwidth. You can use these PLL components to update the output clock frequency,
PLL bandwidth, and phase shift in real time, without reconfiguring the entire FPGA.
2
PLL
PLL
2
3
1
5
1
Output from PLL
GCLK[0..4]
shows using GCLK while cascading PLLs.
20
GCLK[0:19]
Input to PLL
5
2
2
GCLK[15..19]
Control Blocks
GCLK[0:19]
Five Clock
CLK[8..11]
CLK[12..15]
1
20
4
GCLK[10..14]
20
1
Control Blocks
GCLK[0:19]
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Five Clock
GCLK[0:19]
2
2
Output from PLL
GCLK[5..9]
5
20
1
© December 2009 Altera Corporation
PLL
PLL
2
5
4
2
2
CLK[4..7]
4
Output from PLL
Five Clock
Control Blocks
PLL Cascading
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