EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 129

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Figure 2–84. Stratix II GX IOE in DDR Output I/O Configuration
Notes to
(1)
(2)
(3)
Altera Corporation
October 2007
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an
inverter at the OE register data port.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
2–84:
clkout
aclr/apreset
sclr/spreset
ce_out
oe
Chip-Wide Reset
Output Register
Output Register
OE Register
OE Register
ENA
CLRN/PRN
CLRN/PRN
CLRN/PRN
CLRN/PRN
D
ENA
D
ENA
D
ENA
D
Q
Q
Q
Q
Used for
DDR, DDR2
SDRAM
Notes
clk
Stratix II GX Device Handbook, Volume 1
Open-Drain Output
Drive Strength
Pin Delay
(1),
Output
Control
(2)
OE Register
t CO Delay
Stratix II GX Architecture
V CCIO
V CCIO
PCI Clamp (3)
Termination
On-Chip
Bus-Hold
Circuit
Programmable
Pull-Up
Resistor
2–121