EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 113

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Figure 2–73. Global and Regional Clock Connections from Top and Bottom Clock Pins and Enhanced PLL
Outputs
Notes to
(1)
(2)
Altera Corporation
October 2007
EP2SGX30C/D and EP2SGX60C/D devices only have two enhanced PLLs (5 and 6), but the connectivity from these
two PLLs to the global and regional clock networks remains the same as shown.
If the design uses the feedback input, you will lose one (or two, if FBIN is differential) external clock output pin.
Notes
Figure
(1),
2–73:
(2)
Regional
Regional
Clocks
Clocks
Clocks
Global
RCLK27
RCLK26
RCLK25
RCLK24
RCLK10
RCLK11
RCLK8
RCLK9
Figure 2–73
outputs and top and bottom CLK pins.
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
(2)
shows the global and regional clocking from enhanced PLL
(2)
PLL 11
PLL 12
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 6
PLL 5
(2)
(2)
Stratix II GX Device Handbook, Volume 1
RCLK31
RCLK30
RCLK29
RCLK28
G15
G14
G13
G12
G4
G5
G6
G7
RCLK12
RCLK13
RCLK14
RCLK15
Stratix II GX Architecture
2–105