EP20K400CF672C8 Altera, EP20K400CF672C8 Datasheet - Page 24

• Manufacturer Part Number: EP20K400CF672C8
• Description: APEX 20KC
• Manufacturer: Altera

APEX 20KC Programmable Logic Device Data Sheet
24
Row I/O pin
Column I/O
pin
LE
ESB
Local
interconnect
MegaLAB
interconnect
Row
FastTrack
interconnect
Column
FastTrack
interconnect
FastRow
interconnect
Table 8. APEX 20KC Routing Scheme
Source
I/O Pin
Row
v
Column
I/O Pin
v
Product-Term Logic
The product-term portion of the MultiCore architecture is implemented
with the ESB. The ESB can be configured to act as a block of macrocells on
an ESB-by-ESB basis. Each ESB is fed by 32 inputs from the adjacent local
interconnect; therefore, it can be driven by the MegaLAB interconnect or
the adjacent LAB. Also, nine ESB macrocells feed back into the ESB
through the local interconnect for higher performance. Dedicated clock
pins, global signals, and additional inputs from the local interconnect
drive the ESB control signals.
In product-term mode, each ESB contains 16 macrocells. Each macrocell
consists of two product terms and a programmable register.
shows the ESB in product-term mode.
v
LE
ESB
v
Interconnect
Local
v
v
v
v
v
Destination
Interconnect
MegaLAB
v
v
v
v
v
Interconnect
FastTrack
Row
v
v
v
v
Interconnect
FastTrack
Column
v
v
v
v
v
Altera Corporation
Figure 13
Interconnect
FastRow
v