EP20K400CF672C8 Altera, EP20K400CF672C8 Datasheet - Page 11

• Manufacturer Part Number: EP20K400CF672C8
• Description: APEX 20KC
• Manufacturer: Altera

Altera Corporation
Figure 4. LAB Control Signal Generation
Notes to
(1)
(2)
The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the
LAB.
The SYNCCLR signal can be generated by the local interconnect or global signals.
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Figure
Dedicated
Clocks
Global
Signals
4:
The LAB-wide control signals can be generated from the LAB local
interconnect, global signals, and dedicated clock pins. The inherent low
skew of the FastTrack interconnect enables it to be used for clock
distribution.
Logic Element
The LE, the smallest unit of logic in the APEX 20KC architecture, is
compact and provides efficient logic usage. Each LE contains a four-input
LUT, which is a function generator that can quickly implement any
function of four variables. In addition, each LE contains a programmable
register and carry and cascade chains. Each LE drives the local
interconnect, MegaLAB interconnect, and FastTrack interconnect routing
structures. See
4
4
Figure 4
SYNCCLR
or LABCLK2 (2)
Figure
or LABCLKENA2
shows the LAB control signal generation circuit.
SYNCLOAD
5.
APEX 20KC Programmable Logic Device Data Sheet
LABCLK1
LABCLKENA1
LABCLR2 (1)
LABCLR1 (1)
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