EP20K400CF672C7 Altera, EP20K400CF672C7 Datasheet - Page 17

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EP20K400CF672C7

Manufacturer Part Number
EP20K400CF672C7
Description
APEX 20KC
Manufacturer
Altera
Datasheet

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Figure 8. APEX 20KC LE Operating Modes
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
data3 (data)
data1 (5)
data2 (5)
Normal Mode (1)
Arithmetic Mode
Counter Mode
LEs in normal mode support register packing.
There are two LAB-wide clock enables per LAB.
When using the carry-in in normal mode, the packed register feature is unavailable.
A register feedback multiplexer is available on LE1 of each LAB.
The DATA1 and DATA2 input signals can supply counter enable, up or down control, or register feedback signals for
LEs other than the second LE in an LAB.
The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB.
data1
data2
data1
data2
data3
data4
Figure
(4)
8:
Carry-In
Carry-In (3)
Carry-In
3-Input
3-Input
LUT
LUT
3-Input
3-Input
4-Input
LUT
LUT
LUT
Cascade-In
Cascade-In
Carry-Out
Carry-Out
Cascade-In
Cascade-Out
Cascade-Out
Cascade-Out
LAB-Wide
Synchronous
Load (6)
APEX 20KC Programmable Logic Device Data Sheet
LAB-Wide
Clock Enable (2)
LAB-Wide
Synchronous
Clear (6)
LAB-Wide
Clock Enable (2)
LAB-Wide
Clock Enable (2)
D
ENA
CLRN
PRN
D
ENA
CLRN
PRN
Q
ENA
D
Q
CLRN
PRN
Q
LE Out
LE Out
LE Out
LE Out
LE Out
LE Out
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