DSPIC33FJ64MC204T-I/ML Microchip Technology, DSPIC33FJ64MC204T-I/ML Datasheet - Page 18
![16-bit DSC, 64KB Flash,Motor, DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ64MC204T-I/ML
Manufacturer Part Number
DSPIC33FJ64MC204T-I/ML
Description
16-bit DSC, 64KB Flash,Motor, DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64MC204T-I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ64MC204T-I/MLTR
- Current page: 18 of 436
- Download datasheet (6Mb)
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
TABLE 1-1:
DS70291E-page 18
TMS
TCK
TDI
TDO
INDX1
QEA1
QEB1
UPDN1
INDX2
QEA2
QEB2
UPDN2
C1RX
C1TX
RTCC
CV
C1IN-
C1IN+
C1OUT
C2IN-
C2IN+
C2OUT
PMA0
PMA1
PMA2 -PMPA10
PMBE
PMCS1
PMD0-PMPD7
PMRD
PMWR
DAC1RN
DAC1RP
DAC1RM
DAC2RN
DAC2RP
DAC2RM
Legend: CMOS = CMOS compatible input or output
REF
Pin Name
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
PINOUT I/O DESCRIPTIONS (CONTINUED)
Type
Pin
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
TTL/ST
TTL/ST
TTL/ST
Buffer
CMOS
CMOS
Type
ANA
ANA
ANA
ANA
ANA
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PPS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
Quadrature Encoder Index1 Pulse input.
Quadrature Encoder Phase A input in QEI1 mode. Auxiliary Timer
External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI1 mode. Auxiliary Timer
External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
Quadrature Encoder Index2 Pulse input.
Quadrature Encoder Phase A input in QEI2 mode. Auxiliary Timer
External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI2 mode. Auxiliary Timer
External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
Real-Time Clock Alarm Output.
Comparator Voltage Reference Output.
Comparator 1 Negative Input.
Comparator 1 Positive Input.
Comparator 1 Output.
Comparator 2 Negative Input.
Comparator 2 Positive Input.
Comparator 2 Output.
Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and
Output (Master modes).
Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and
Output (Master modes).
Parallel Master Port Address (Demultiplexed Master Modes).
Parallel Master Port Byte Enable Strobe.
Parallel Master Port Chip Select 1 Strobe.
Parallel Master Port Data (Demultiplexed Master mode) or Address/
Data (Multiplexed Master modes).
Parallel Master Port Read Strobe.
Parallel Master Port Write Strobe.
DAC1 Negative Output.
DAC1 Positive Output.
DAC1 Output indicating middle point value (typically 1.65V).
DAC2 Negative Output.
DAC2 Positive Output.
DAC2 Output indicating middle point value (typically 1.65V).
Analog = Analog input
O = Output
TTL = TTL input buffer
Description
© 2011 Microchip Technology Inc.
P = Power
I = Input
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