DSPIC33FJ256MC510A-E/PF Microchip Technology, DSPIC33FJ256MC510A-E/PF Datasheet - Page 4

• Manufacturer Part Number: DSPIC33FJ256MC510A-E/PF
• Description: 16 Bit MCU/DSP 40MIPS 256KB FLASH 100 TQFP 14x14x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256MC510A-E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC33FJ256MCX06A/X08A/X10A
4. Module: QEI
5. Module: UART
6. Module: ADC
DS80484D-page 4
When the TQCS and TQGATE bits in the
QEIxCON register are set, the POSCNT counter
should not increment but erroneously does, and if
allowed to increment to match MAXCNT, a QEI
interrupt will be generated.
Work around
To prevent the erroneous increment of POSCNT
while
Accumulation mode, initialize MAXCNT = 0.
Affected Silicon Revisions
The UART module will not generate consecutive
break characters. Trying to perform a back-to-back
Break character transmission will cause the UART
module to transmit the dummy character used to
generate the first Break character instead of
transmitting the second Break character. Break
characters are generated correctly if they are
followed by non-Break character transmission.
Work around
None.
Affected Silicon Revisions
The
(ADxCON1<0>) does not indicate completion of
conversion when External Interrupt is selected as
the ADC trigger source (ADxCON1<SSRC> = 1).
Work around
Use an ADC interrupt or poll ADxIF bit in the IFSx
registers
conversion.
Affected Silicon Revisions
A2
A2
A2
X
X
X
ADC
running
A3
A3
A3
X
X
X
to
Conversion
determine
the
QEI
Status
the
in
completion
Timer
(DONE)
Gated
bit
of
7. Module: SPI
8. Module: DMA Controller
Writing to the SPIxBUF register as soon as the
TBF bit is cleared will cause the SPI module to
ignore the written data. Applications that use SPI
with DMA are not affected by this erratum.
Work around
After the TBF bit is cleared, wait for a minimum
duration of one SPI clock before writing to the
SPIxBUF register.
Alternately, do one of the following:
• Poll the RBF bit and wait for it to get set before
• Poll the SPI Interrupt flag and wait for it to get
• Use an SPI Interrupt Service Routine
• Use DMA
Affected Silicon Revisions
DMA CPU write collisions will not be detected, and
the corresponding XWCOLn bit (n = 0, 1, …, 7) will
not be set. As a result, a CPU write collision event
will not generate a DMA Error Trap.
Work around
None. Before writing to any memory location in
DMA RAM, ensure that none of the enabled DMA
channels is using the same memory location for
data transfers from a peripheral.
A2
A2
writing to the SPIxBUF register
set before writing to the SPIxBUF register
X
A3
A3
X
X
© 2010 Microchip Technology Inc.