DSPIC33FJ256MC510A-E/PF Microchip Technology, DSPIC33FJ256MC510A-E/PF Datasheet - Page 2

• Manufacturer Part Number: DSPIC33FJ256MC510A-E/PF
• Description: 16 Bit MCU/DSP 40MIPS 256KB FLASH 100 TQFP 14x14x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256MC510A-E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC33FJ256MCX06A/X08A/X10A
TABLE 2:
DS80484D-page 2
Note 1:
Controller
Module
ECAN
ECAN
UART
DMA
ADC
ADC
QEI
QEI
SPI
All
Only those issues indicated in the last column apply to the current silicon revision.
Accumulation
Accumulation
Consumption
Timer Gated
Timer Gated
Characters
CPU Write
WAKIF bit
Operation
Detection
DONE bit
Collision
Feature
in Sleep
SILICON ISSUE SUMMARY
Current
TBF bit
150ºC
Break
Mode
DMA
Number
Item
10.
1.
2.
3.
4.
5.
6.
7.
8.
9.
The WAKIF bit in the CxINTF register cannot be cleared by
software instruction after the device is interrupted from Sleep
due to activity on the CAN bus.
False DMA Error Traps may be generated in applications that
perform both transmissions and receptions using ECAN with
DMA.
When Timer Gated Accumulation is enabled, the QEI does not
generate an interrupt on every falling edge.
When Timer Gated Accumulation is enabled, and an external
signal is applied, the POSCNT increments and generates an
interrupt after a match with MAXCNT.
The UART module will not generate consecutive break
characters.
The ADC Conversion Status bit (DONE) does not work when
External Interrupt is selected as the ADC trigger source.
Writing to the SPIBUF register as soon as the TBF bit is
cleared will cause the SPI module to ignore the written data.
DMA CPU write collisions will not be detected.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
may exceed the device data sheet specifications.
Affected revisions of silicon only support 140ºC operation
instead of 150ºC for extended operating temperature.
Issue Summary
PD
© 2010 Microchip Technology Inc.
) of the device
Revisions
A2
Affected
X
X
X
X
X
X
X
X
X
A3
X
X
X
X
X
X
X
X
X
(1)