DSPIC33FJ128MC204-E/PT Microchip Technology, DSPIC33FJ128MC204-E/PT Datasheet - Page 134
![16-bit DSC, 128KB Flash,Motor,DMA,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY](/photos/6/82/68251/c04-076_pt_sml.jpg)
DSPIC33FJ128MC204-E/PT
Manufacturer Part Number
DSPIC33FJ128MC204-E/PT
Description
16-bit DSC, 128KB Flash,Motor,DMA,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128MC204-E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128MC204-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
The DMA controller features eight identical data
transfer channels.
Each channel has its own set of control and status
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
The DMA controller supports the following features:
• Eight DMA channels
• Register Indirect With Post-increment Addressing
• Register Indirect Without Post-increment
• Peripheral Indirect Addressing mode (peripheral
• CPU interrupt after half or full block transfer
FIGURE 8-1:
DS70291E-page 134
mode
Addressing mode
generates destination address)
complete
SRAM
Note:
SRAM X-Bus
CPU
CPU and DMA address buses are not shown for clarity.
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
PORT 1
DMA RAM
CPU Peripheral DS Bus
Peripheral
Non-DMA
PORT 2
Ready
DMA DS Bus
DMA Controller
• Byte or word transfers
• Fixed priority channel arbitration
• Manual (software) or Automatic (peripheral DMA
• One-Shot or Auto-Repeat block transfer modes
• Ping-Pong mode (automatic switch between two
• DMA request for each channel can be selected
• Debug support features
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
requests) transfer initiation
DPSRAM start addresses after each block
transfer complete)
from any supported interrupt source
Channels
DMA
Peripheral Indirect Address
Peripheral 1
CPU
Ready
DMA
© 2011 Microchip Technology Inc.
DMA
Peripheral 3
CPU
Ready
DMA
DMA
Peripheral 2
CPU
Ready
DMA
DMA
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