DSPIC33EP256MU810-I/PT Microchip Technology, DSPIC33EP256MU810-I/PT Datasheet - Page 553

• Manufacturer Part Number: DSPIC33EP256MU810-I/PT
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-I/PT

• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 83
• Flash Memory Size: 280KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Processor Series: DSPIC33E
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Details

TABLE A-1:
 2009-2011 Microchip Technology Inc.
Section 7.0 “Interrupt Controller” Added the VAR bit (CORCON<15>) to the Core Control Register (see
Section 8.0 “Direct Memory
Access (DMA)”
Section 9.0 “Oscillator
Configuration”
Section 10.0 “Power-Saving
Features”
Section 11.0 “I/O Ports”
Section 12.0 “Timer1”
Section 14.0 “Input Capture”
Section 15.0 “Output Compare”
Section 16.0 “High-Speed PWM
Module (dsPIC33EPXXXMU806/
810/814 Devices Only)”
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
Section Name
MAJOR SECTION UPDATES (CONTINUED)
Register 7-2)
Changed the default POR value for the GIE bit (INTCON2<15) to R/W-1 (see
Register 7-4).
Changed the VECNUM<7:0> = 11111111 pending interrupt vector number to
263 in the Interrupt Control and Status Register (see Register 7-7).
Updated Section 8.1 “DMAC Registers”.
Updated DMA Controller in Figure 8-1.
Added Note 1 to the DMA Channel x Peripheral Address Register (see
Register 8-7).
Added Note 1 and Note 2 to the DMA Channel x Transfer Count Register (see
Register 8-8).
Updated all RQCOLx bit definitions, changing Peripheral Write to Transfer
Request in the DMA Request Collision Status Register (see Register 8-12).
Added the Reference Oscillator Control Register (see Register 9-7).
Added Note 3 and 4 to the CLKDIV Register (see Register 9-2)
Added the DCIMD and C2MD bits to the Peripheral Module Disable Control
Register 1 (see Register 10-1)
Added the IC6MD, IC5MD, IC4MD, IC3MD, OC8MD, OC7MD, OC6MD, and
OC5MD bits to the Peripheral Module Disable Control Register 2 (see
Register 10-2)
Added the T9MD, T8MD, T7MD, and T6MD bits and removed the DSC1MD bit
in the Peripheral Module Disable Control Register 3 (see Register 10-3).
Added the REFOMD bit (PMD4<3>) to the Peripheral Module Disable Control
Register 4 (see Register 10-4).
Updated the first paragraph of Section 11.2 “Configuring Analog and Digital
Port Pins”.
Updated the PWM Fault, Dead Time Compensation, and Synch Input register
numbers of the Selectable Input Sources (see Table 11-2).
Removed RPINR22 register.
Bit names and definitions were modified in the following registers:
• Peripheral Pin Select Input Register 37 (see Register 11-37)
• Peripheral Pin Select Input Register 38 (see Register 11-38)
• Peripheral Pin Select Input Register 39 (see Register 11-39)
• Peripheral Pin Select Input Register 40 (see Register 11-40)
• Peripheral Pin Select Input Register 41 (see Register 11-41)
• Peripheral Pin Select Input Register 42 (see Register 11-42)
• Peripheral Pin Select Input Register 43 (see Register 11-43)
Added Note in Register 12-1.
Added Note 1 to the Input Capture Block Diagram (see Figure 14-1).
Added Note 1 to the Output Compare Module Block Diagram (see Figure 15-1).
Added Note 2 to the Output Compare x Control Register 2 (see Register 15-2).
Added Comparator bit values for the CLSRC<4:0> and FLTSRC<4:0> bits in
the PWM Fault Current-Limit Control Register (see Register 16-21).
Preliminary
Update Description
DS70616E-page 553