DSPIC30F2010T-30I/MM Microchip Technology, DSPIC30F2010T-30I/MM Datasheet - Page 130
![IC,DSP,16-BIT,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC30F2010T-30I/MM
Manufacturer Part Number
DSPIC30F2010T-30I/MM
Description
IC,DSP,16-BIT,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F2010-20ISO.pdf
(202 pages)
3.DSPIC30F2010-20ISO.pdf
(6 pages)
4.DSPIC30F2010-20ISO.pdf
(26 pages)
Specifications of DSPIC30F2010T-30I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC30F2011-20IP PDF datasheet
- DSPIC30F2010-20ISO PDF datasheet #2
- DSPIC30F2010-20ISO PDF datasheet #3
- DSPIC30F2010-20ISO PDF datasheet #4
- Current page: 130 of 202
- Download datasheet (3Mb)
dsPIC30F2010
Table 19-5
Register. Since the control bits within the RCON regis-
ter are R/W, the information in the table implies that all
the bits are negated prior to the action specified in the
condition column.
TABLE 19-5:
Table 19-6
conditions for the RCON Register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 19-6:
DS70118J-page 130
Power-on Reset
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
Interrupt Wake-up from
Sleep
Clock Failure Trap
Trap Reset
Illegal Operation Trap
Note 1:
Power-on Reset
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
Interrupt Wake-up from
Sleep
Clock Failure Trap
Trap Reset
Illegal Operation Reset
Legend: u = unchanged
Note 1:
Condition
Condition
shows the Reset conditions for the RCON
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
shows a second example of the bit
INITIALIZATION CONDITION FOR RCON REGISTER CASE 1
INITIALIZATION CONDITION FOR RCON REGISTER CASE 2
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000004
0x000000
0x000000
Program
PC + 2
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000004
0x000000
0x000000
Counter
Program
PC + 2
Counter
PC + 2
PC + 2
(1)
(1)
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
0
0
0
0
0
0
0
0
0
0
1
0
0
u
u
u
u
u
u
u
u
u
1
u
0
0
0
0
0
0
0
0
0
0
0
1
0
u
u
u
u
u
u
u
u
u
u
1
0
u
1
0
1
1
0
u
u
u
u
u
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
u
0
1
u
u
0
u
u
u
u
u
0
0
0
0
0
0
1
1
0
0
0
0
0
u
0
0
0
0
1
1
u
u
u
u
© 2011 Microchip Technology Inc.
0
0
0
0
0
1
0
0
0
0
0
0
0
u
0
0
0
1
0
u
u
u
u
u
0
0
0
0
1
0
0
1
1
0
0
0
0
u
0
0
1
0
0
1
1
u
u
u
1
0
0
0
0
0
0
0
0
0
0
0
1
0
u
u
u
u
u
u
u
u
u
u
1
1
0
0
0
0
0
0
0
0
0
0
1
1
u
u
u
u
u
u
u
u
u
u
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