DSPIC30F2010T-30I/MM Microchip Technology, DSPIC30F2010T-30I/MM Datasheet
DSPIC30F2010T-30I/MM
Specifications of DSPIC30F2010T-30I/MM
Related parts for DSPIC30F2010T-30I/MM
DSPIC30F2010T-30I/MM Summary of contents
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... Refer to the “dsPIC30F Flash Programming Specification” (DS70102) for detailed information on Device and Revision IDs for your specific device. © 2010 Microchip Technology Inc. dsPIC30F2010 dsPIC30F2010 Family For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkit™ ...
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... An interrupt occurring immediately after modifying the CPU IPL, interrupt IPL, interrupt enable or interrupt flag may cause an address error trap PLL mode is used, the input frequency range is 5 MHz-10 MHz instead of 4 MHz-10 MHz. Affected (1) Revisions © 2010 Microchip Technology Inc. ...
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... Operation Memory Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2010 Microchip Technology Inc. Issue Summary When enabled, the SPI module does not disable RF2 as a general I/O pin. The Quadrature Encoder Interface (QEI) module does not generate an interrupt in a particular overflow condition ...
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... POSCNT increments and generates an interrupt after a match with MAXCNT. If the ADC module enabled state when the device enters Sleep Mode, the power-down current ( the device may exceed the device data sheet PD specifications. Affected (1) Revisions this © 2010 Microchip Technology Inc. ...
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... W10 MOV W2, [W0++] ;Perform indirect ;write via W0 to ;address >= 0x900 MAC W4*W5, A, [W10]+=2, W5 ;Perform ;read operation ;using Y-AGU © 2010 Microchip Technology Inc. dsPIC30F2010 Work arounds Work around 1: Insert a NOP between the two instructions as shown in Example 2. EXAMPLE 2: CORRECT RESULTS ...
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... BCD number mov.b #0x80, w1 ;Second BCD number add.b w0, w1, w2 ;Perform addition bra NC, L0 ;If C set daw.b w2 ;If not,do DAW and bset.b SR, #C ;set the carry bit bra L1 ;and exit L0:daw.b w2 L1: .... Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... RAM register prior to performing the operations listed in Table 3. The work around for Example 4 is demonstrated in © 2010 Microchip Technology Inc. These instructions are identified in Example 4 occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F2010 devices. ...
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... DISI BEFORE RETFIE ;Timer1 ISR ;This line optional ;This line optional ;Another interrupt occurs ;here and it is processed ;correctly Example 8. This will disable all RAISE IPL BEFORE RETFIE ;Timer1 ISR ;Another interrupt occurs ;here and it is processed ;correctly © 2010 Microchip Technology Inc. ...
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... © 2010 Microchip Technology Inc. 9. Module: Output Compare If the desired duty cycle is ‘0’ (OCxRS = 0), the module will generate a high level glitch counter The second problem is that on the next cycle after DISI the glitch, the OC pin does not go high other words, it misses the next compare for any value written on OCxRS ...
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... POST<1:0> Oscillator Postscaler Control bits (OSCCON<7:6>). 2. Use the EC without PLL Clock mode with a suitable equivalent 4x PLL clock rate. Affected Silicon Revisions 2.5V-3.0V, the 4x PLL input DD is 3.0V-3.6V, the 4x PLL input DD clock frequency to obtain the © 2010 Microchip Technology Inc. ...
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... SET_AND_SAVE_CPU_IPL (save_to RESTORE_CPU_IPL (save_to) © 2010 Microchip Technology Inc. dsPIC30F2010 Work around 2: For C Language Source Code For applications using the C language, MPLAB C Compiler for dsPIC DSCs versions 1.32 and higher, provide several macros for modifying the CPU IPL. The SET_CPU_IPL macro provides the ...
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... RF2 pin when the SPIEN bit is set. This means that RF2 can be used as general I/O when the SPI module is enabled. Work around It is recommended to avoid using the RF2 pin as I/O if the SPIEN bit is set. Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... User's code MAXCNT = 0x7FFF; Motor_Position = POSCNT_b15 + POSCNT; // ... User's code } void __attribute__((__interrupt__)) _QEIInterrupt(void) { IFSxbits.QEIIF = 0; POSCNT_b15 ^= 0x8000; // Overflow or Underflow } © 2010 Microchip Technology Inc. shows the // Instead of 0xFFFF // Clear QEI interrupt flag // x=2 for dsPIC30F // x=3 for dsPIC33F dsPIC30F2010 DS80451E-page 13 ...
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... GotoSleep( ) function call. This ensures that the device continues executing the correct code sequence after waking up from Sleep mode. Example 14 described above. ; Ensure flag is reset ; Return from Interrupt Service Routine the function call would be demonstrates the work around © 2010 Microchip Technology Inc. ...
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... Note: The above work around is recommended for users for whom application hardware changes are not possible. © 2010 Microchip Technology Inc. Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz LPRC with a 64:1 postscaler mode ...
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... If the D_A flag and the I2COV flag are both set, a valid data byte was received and a previous valid data byte was lost. It will be necessary to code for handling this overflow condition. Affected Silicon Revisions © 2010 Microchip Technology Inc slave interrupt 2 C nodes receive 2 C data 2 C nodes. This A4 X ...
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... Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F2010 2 24. Module there are two I C devices on the bus, one of them acts as the master receiver and the other acts as the slave transmitter. If both devices are configured for 10-bit addressing mode, and have ...
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... C module is configured as a 10-bit slave with an address of 0x102, the I2CxRCV register content for the lower address byte is 0x01, rather than 0x02. However, the acknowledges both address bytes. Work around None. Affected Silicon Revisions © 2010 Microchip Technology Inc. with the module ...
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... © 2010 Microchip Technology Inc. 31. Module: Program Flash Memory When performing Run-Time Self-Programming (RTSP) operations on program Flash memory or write operations on Data EEPROM, the device automatically times the erase/write operation. For this revision of silicon, this method of timing the erase/write operation is not supported. ...
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... MIPS. This may be easily performed at any time via the Oscillator Postscaler bits (POST), (OSCCON<7:6>), that allow the application to divide the system clock down by a factor 64. Affected Silicon Revisions © 2010 Microchip Technology Inc. in order to ...
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... Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F2010 36. Module: Sleep Mode of approximately 100 μA. The device exhibits I PD Work around If the application does not use the on-chip A/D converter possible to reduce the I below 0.1 μA. The following additional measures need to be taken in these circumstances: 1 ...
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... ADC module by setting the ADC Module Disable bit in the corresponding Peripheral Module Disable register (PMDx), prior to executing a PWRSAV instruction. Affected Silicon Revisions DS80451E-page 22 Timer Gated specifications #0 © 2010 Microchip Technology Inc. ...
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... Note 1: Base I is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and PD pulled high. LVD, BOR, WDT, etc. are all switched off. © 2010 Microchip Technology Inc. dsPIC30F2010 specifica- IL Standard Operating Conditions: 3.3V and 5.0V (±10%) (unless otherwise stated) -40° ...
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... Rev D Document (6/2010) Added silicon issue 39 (ADC) and data sheet clarification 1 (DC Characteristics: I/O Pin Input Specifications). Rev E Document (10/2010) Added data sheet clarification 2 (DC Characteristics: Power-Down Current (I )). PD DS80451E-page 24 Operations), (Interrupt (Sleep C), EEPROM), 33 EEPROM), 35 © 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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